### Abstract

We present an ordered tree (O-tree) structure to represent nonslicing floorplans. The O-tree uses only n (2 + [lg n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both X and y directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is 0(n!2 ^{2n-2}/n ^{1.5}). This is very concise compared to a sequence pair representation that has O((n!) ^{2}) combina-tions. The approximate ratio of sequence pair and O-tree combinations is O(n ^{2}(n/4e) ^{n}). The complexity of an O-tree is even smaller than a binary tree structure for a slicing floorplan that has O(n!2 ^{5n-3}/n ^{1.5}) combinations. Given an O-tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O-tree. Empirical results on MCNC (www.mcnc.org) benchmarks show promising performance with average 16% improvement in wire length and 1% less dead space over the previous central processing unit (CPU) intensive cluster refinement method.

Original language | English |
---|---|

Pages (from-to) | 26-29 |

Number of pages | 4 |

Journal | IEEE Circuits and Systems Magazine |

Volume | 3 |

Issue number | 2 |

DOIs | |

Publication status | Published - 2003 Jun |

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### ASJC Scopus subject areas

- Engineering(all)
- Hardware and Architecture

### Cite this

*IEEE Circuits and Systems Magazine*,

*3*(2), 26-29. https://doi.org/10.1109/MCAS.2003.1242834

**Floorplanning using a tree representation : A summary.** / Takahashi, T.; Guo, P. N.; Cheng, C. K.; Yoshimura, T.

Research output: Contribution to journal › Article

*IEEE Circuits and Systems Magazine*, vol. 3, no. 2, pp. 26-29. https://doi.org/10.1109/MCAS.2003.1242834

}

TY - JOUR

T1 - Floorplanning using a tree representation

T2 - A summary

AU - Takahashi, T.

AU - Guo, P. N.

AU - Cheng, C. K.

AU - Yoshimura, T.

PY - 2003/6

Y1 - 2003/6

N2 - We present an ordered tree (O-tree) structure to represent nonslicing floorplans. The O-tree uses only n (2 + [lg n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both X and y directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is 0(n!2 2n-2/n 1.5). This is very concise compared to a sequence pair representation that has O((n!) 2) combina-tions. The approximate ratio of sequence pair and O-tree combinations is O(n 2(n/4e) n). The complexity of an O-tree is even smaller than a binary tree structure for a slicing floorplan that has O(n!2 5n-3/n 1.5) combinations. Given an O-tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O-tree. Empirical results on MCNC (www.mcnc.org) benchmarks show promising performance with average 16% improvement in wire length and 1% less dead space over the previous central processing unit (CPU) intensive cluster refinement method.

AB - We present an ordered tree (O-tree) structure to represent nonslicing floorplans. The O-tree uses only n (2 + [lg n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both X and y directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is 0(n!2 2n-2/n 1.5). This is very concise compared to a sequence pair representation that has O((n!) 2) combina-tions. The approximate ratio of sequence pair and O-tree combinations is O(n 2(n/4e) n). The complexity of an O-tree is even smaller than a binary tree structure for a slicing floorplan that has O(n!2 5n-3/n 1.5) combinations. Given an O-tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O-tree. Empirical results on MCNC (www.mcnc.org) benchmarks show promising performance with average 16% improvement in wire length and 1% less dead space over the previous central processing unit (CPU) intensive cluster refinement method.

UR - http://www.scopus.com/inward/record.url?scp=2942640191&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=2942640191&partnerID=8YFLogxK

U2 - 10.1109/MCAS.2003.1242834

DO - 10.1109/MCAS.2003.1242834

M3 - Article

AN - SCOPUS:2942640191

VL - 3

SP - 26

EP - 29

JO - IEEE Circuits and Systems Magazine

JF - IEEE Circuits and Systems Magazine

SN - 1531-636X

IS - 2

ER -