Floorplanning with constraint extraction based on interconnecting information analysis

Jiayi Liu, Sheqin Dong, Xianlong Hong, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

After the phase of high level synthesis, a lot of design information is hidden for the floorplanning process. As a result, the floorplanning process which is only aiming at decreasing area and wirelength may cause design failure for the circuits, because of ignoring some hidden constraints. In this paper, we propose a method to extract some geometric constraints based on interconnecting information analysis. And a new floorplanning algorithm with CBL representation which can handle these constraints is also proposed. And the final experimental results prove the effectiveness of our method.

Original languageEnglish
Title of host publicationASICON 2007 - 2007 7th International Conference on ASIC Proceeding
Pages1084-1087
Number of pages4
DOIs
Publication statusPublished - 2007
Event2007 7th International Conference on ASIC, ASICON 2007 - Guilin
Duration: 2007 Oct 262007 Oct 29

Other

Other2007 7th International Conference on ASIC, ASICON 2007
CityGuilin
Period07/10/2607/10/29

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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