Folding of logic functions and its application to look up table compaction

Shinji Kimura, Takashi Horiyama, Masaki Nakanishi, Hirotsugu Kajihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

The paper describes the folding method of logic functions to reduce the size of memories for keeping the functions. The folding is based on the relation of fractions of logic functions. We show that the fractions of the full adder function have the bit-wise NOT relation and the bit-wise OR relation, and that the memory size becomes half (8-bit). We propose a new 3-1 LUT with the folding mechanisms which can implement a full adder with one LUT. A fast carry propagation line is introduced for a multi-bit addition. The folding and fast carry propagation mechanisms are shown to be useful to implement other multi-bit operations and general 4 input functions without extra hardware resources. The paper shows the reduction of the area consumption when using our LUTs compared to the case using 4-1 LUTs on several benchmark circuits.

Original languageEnglish
Title of host publicationIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Pages694-697
Number of pages4
DOIs
Publication statusPublished - 2002
EventIEEE/ACM International Conference on Computer Aided Design (ICCAD) - San Jose, CA, United States
Duration: 2002 Nov 102002 Nov 14

Other

OtherIEEE/ACM International Conference on Computer Aided Design (ICCAD)
CountryUnited States
CitySan Jose, CA
Period02/11/1002/11/14

Fingerprint

Compaction
Adders
Data storage equipment
Hardware
Networks (circuits)

ASJC Scopus subject areas

  • Software

Cite this

Kimura, S., Horiyama, T., Nakanishi, M., & Kajihara, H. (2002). Folding of logic functions and its application to look up table compaction. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (pp. 694-697) https://doi.org/10.1145/774572.774674

Folding of logic functions and its application to look up table compaction. / Kimura, Shinji; Horiyama, Takashi; Nakanishi, Masaki; Kajihara, Hirotsugu.

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 2002. p. 694-697.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kimura, S, Horiyama, T, Nakanishi, M & Kajihara, H 2002, Folding of logic functions and its application to look up table compaction. in IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. pp. 694-697, IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, CA, United States, 02/11/10. https://doi.org/10.1145/774572.774674
Kimura S, Horiyama T, Nakanishi M, Kajihara H. Folding of logic functions and its application to look up table compaction. In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 2002. p. 694-697 https://doi.org/10.1145/774572.774674
Kimura, Shinji ; Horiyama, Takashi ; Nakanishi, Masaki ; Kajihara, Hirotsugu. / Folding of logic functions and its application to look up table compaction. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers. 2002. pp. 694-697
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