Formula-based method for capacitance extraction of interconnects with dummy fills

Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda

    Research output: Contribution to journalArticle

    1 Citation (Scopus)

    Abstract

    In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.

    Original languageEnglish
    Pages (from-to)847-855
    Number of pages9
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE89-A
    Issue number4
    DOIs
    Publication statusPublished - 2006 Apr

    Fingerprint

    Interconnect
    Capacitance
    VLSI Circuits
    VLSI Design
    Timing Analysis
    Structural Parameters
    VLSI circuits
    3D
    Application specific integrated circuits
    High Accuracy
    Metals
    Design
    Unit
    Evaluate

    Keywords

    • Capacitance extraction
    • Capacitance formula
    • Dummy fill
    • Interconnect

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

    Formula-based method for capacitance extraction of interconnects with dummy fills. / Kurokawa, Atsushi; Kasebe, Akira; Kanamoto, Toshiki; Yang, Yun; Huang, Zhangcai; Inoue, Yasuaki; Masuda, Hiroo.

    In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E89-A, No. 4, 04.2006, p. 847-855.

    Research output: Contribution to journalArticle

    Kurokawa, Atsushi ; Kasebe, Akira ; Kanamoto, Toshiki ; Yang, Yun ; Huang, Zhangcai ; Inoue, Yasuaki ; Masuda, Hiroo. / Formula-based method for capacitance extraction of interconnects with dummy fills. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2006 ; Vol. E89-A, No. 4. pp. 847-855.
    @article{981fcd6e26c64c52a963bbe3f06b7898,
    title = "Formula-based method for capacitance extraction of interconnects with dummy fills",
    abstract = "In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3{\%} error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.",
    keywords = "Capacitance extraction, Capacitance formula, Dummy fill, Interconnect",
    author = "Atsushi Kurokawa and Akira Kasebe and Toshiki Kanamoto and Yun Yang and Zhangcai Huang and Yasuaki Inoue and Hiroo Masuda",
    year = "2006",
    month = "4",
    doi = "10.1093/ietfec/e89-a.4.847",
    language = "English",
    volume = "E89-A",
    pages = "847--855",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "4",

    }

    TY - JOUR

    T1 - Formula-based method for capacitance extraction of interconnects with dummy fills

    AU - Kurokawa, Atsushi

    AU - Kasebe, Akira

    AU - Kanamoto, Toshiki

    AU - Yang, Yun

    AU - Huang, Zhangcai

    AU - Inoue, Yasuaki

    AU - Masuda, Hiroo

    PY - 2006/4

    Y1 - 2006/4

    N2 - In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.

    AB - In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects with dummy fills for VLSI designs. The whole flow is as follows: 1) in each process, obtain capacitances per unit length using a 3-D field solver and then create formulas, and 2) in the actual design phase, execute a well-known 2.5-D capacitance extraction. Our results indicated that accuracies of the proposed formulas were almost within 3% error. The proposed formula-based method can extract interconnect capacitances with high accuracy for VLSI circuits. Moreover, we present formulas to evaluate the effect of dummy fills on interconnect capacitances. These can be useful for determining design guidelines, such as metal density before the actual design, and for analyzing the effect of each structural parameter during the design phase.

    KW - Capacitance extraction

    KW - Capacitance formula

    KW - Dummy fill

    KW - Interconnect

    UR - http://www.scopus.com/inward/record.url?scp=33646263101&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=33646263101&partnerID=8YFLogxK

    U2 - 10.1093/ietfec/e89-a.4.847

    DO - 10.1093/ietfec/e89-a.4.847

    M3 - Article

    AN - SCOPUS:33646263101

    VL - E89-A

    SP - 847

    EP - 855

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 4

    ER -