TY - GEN
T1 - FPGA-based Heterogeneous Solver for Three-Dimensional Routing
AU - Hasegawa, Kento
AU - Ishikawa, Ryota
AU - Nishizawa, Makoto
AU - Kawamura, Kazushi
AU - Tawada, Masashi
AU - Togawa, Nozomu
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/1
Y1 - 2020/1
N2 - A heuristic algorithm is one of the approaches to solve an NP-hard problem. In order to enhance the capability of the system, heterogeneous computing is often adapted. In this paper, we propose an FPGA-based heterogeneous solver for three-dimensional routing. The proposed system is implemented into multiple FPGA boards and a single-board computer. The experimental results demonstrate that the proposed system outperforms a single FPGA system.
AB - A heuristic algorithm is one of the approaches to solve an NP-hard problem. In order to enhance the capability of the system, heterogeneous computing is often adapted. In this paper, we propose an FPGA-based heterogeneous solver for three-dimensional routing. The proposed system is implemented into multiple FPGA boards and a single-board computer. The experimental results demonstrate that the proposed system outperforms a single FPGA system.
UR - http://www.scopus.com/inward/record.url?scp=85083035938&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85083035938&partnerID=8YFLogxK
U2 - 10.1109/ASP-DAC47756.2020.9045660
DO - 10.1109/ASP-DAC47756.2020.9045660
M3 - Conference contribution
AN - SCOPUS:85083035938
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 11
EP - 12
BT - ASP-DAC 2020 - 25th Asia and South Pacific Design Automation Conference, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020
Y2 - 13 January 2020 through 16 January 2020
ER -