FPGA-based reconfigurable adaptive FEC

Kazunori Shimizu, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Contribution to journalArticle

    2 Citations (Scopus)

    Abstract

    In this paper, we propose a reconfigurable adaptive FEC system. In adaptive FEC schemes, the error correction capability t is changed dynamically according to the communication channel condition. If a particular error correction capability t is given, we can implement an FEC decoder which is optimal for t by taking the number of operations into consideration. Thus, reconfiguring the optimal FEC decoder dynamically for each error correction capability allows us to maximize the throughput of each decoder within a limited hardware resource. Based on this concept, our reconfigurable adaptive FEC system can reduce the packet dropping rate more efficiently than conventional fixed hardware systems. We can improve data transmission throughput for a reliable transport protocol. Practical simulation results are also shown.

    Original languageEnglish
    Pages (from-to)3036-3046
    Number of pages11
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE87-A
    Issue number12
    Publication statusPublished - 2004 Dec

    Fingerprint

    Error correction
    Error Correction
    Field Programmable Gate Array
    Field programmable gate arrays (FPGA)
    Reconfigurable Systems
    Adaptive systems
    Adaptive Systems
    Throughput
    Hardware
    Communication channels (information theory)
    Transport Protocol
    Communication Channels
    Data Transmission
    Data communication systems
    Maximise
    Resources
    Simulation

    Keywords

    • Adaptive FEC
    • Dynamic reconfigurable system
    • FPGA
    • Reed Solomon codes

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

    FPGA-based reconfigurable adaptive FEC. / Shimizu, Kazunori; Uchida, Jumpei; Miyaoka, Yuichiro; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E87-A, No. 12, 12.2004, p. 3036-3046.

    Research output: Contribution to journalArticle

    Shimizu, Kazunori ; Uchida, Jumpei ; Miyaoka, Yuichiro ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / FPGA-based reconfigurable adaptive FEC. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2004 ; Vol. E87-A, No. 12. pp. 3036-3046.
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