FPGA-based SHA-3 acceleration on a 32-bit processor via instruction set extension

Yi Wang, Youhua Shi, Chao Wang, Yajun Ha

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)

    Abstract

    As embedded systems play more and more important roles Internet of Things (IoT), the integration of cryptographic functionalities is an urgent demand to ensure data and information security. Recently, Keccak was declared as the winner of the third generation of Secure Hashing Algorithm (SHA-3). However, implementing SHA-3 on a specific 32-bit processor failed to meet the performance requirement. On the other hand, implementing it as a cryptographic coprocessor consumes a lot of extra area and requires customized driver program. Although implementing Keccak on a 64-bit platform is more efficient, this platform is not suitable for embedded implementation. In this paper, we propose a novel SHA-3 implementation using instruction set extension based on a 32-bit LEON3 processor (an open source processor), with the goals of reducing execution cycles and code size. Experimental results show that the proposed design reduces around 87% execution cycles and 10.5% code size as compared to reference designs. Our design takes up only 9.44% extra area with negligible speed overhead compared to the standard LEON3 processor. Compared to the existing hardware accelerators, our proposed design occupies only half of area resources and does not require extra driver programs to be developed when integrated into the overall system.

    Original languageEnglish
    Title of host publicationProceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages305-308
    Number of pages4
    ISBN (Print)9781479983636
    DOIs
    Publication statusPublished - 2015 Sep 30
    Event11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore
    Duration: 2015 Jun 12015 Jun 4

    Other

    Other11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
    CountrySingapore
    CitySingapore
    Period15/6/115/6/4

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    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Wang, Y., Shi, Y., Wang, C., & Ha, Y. (2015). FPGA-based SHA-3 acceleration on a 32-bit processor via instruction set extension. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 (pp. 305-308). [7285111] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2015.7285111