FPGA implementation of high frame rate and ultra-low delay tracking with local-search based block matching

Tingting Hu, Hong Wu, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

As more and more human-machine interactive applications call for higher frame rate and lower delay to get a better experience, there is an inevitable need for high frame rate and ultra-low delay image processing system. Current existing works based on vision chip target on video with simple patterns or simple shapes in order to get a higher speed, which is reasonable in the first trial of this new field. However, more complicated system is required for real-life applications. This paper proposes a KLT (Kanade-Lucas-Tomasi) based tracking system with high frame rate and ultra-low delay, implemented on FPGA board. And based on the framework of KLT, local maximum neighboring check, local-search based SAD (Sum of Absolute Difference) block matching and coordinate-addressed feature storage are proposed to localize the whole algorithm. In a broader framework, the whole system is made parallelized and pipelined in order to get a high throughput which can meet the high frame rate and ultra-low delay system's demand. Evaluation results show that the proposed hardware system can work at 784fps and 0.762ms delay with resolution of 640×480.

Original languageEnglish
Title of host publicationProceedings - 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages93-98
Number of pages6
ISBN (Electronic)9781509049936
DOIs
Publication statusPublished - 2017 Mar 14
Event2017 International Conference on Machine Vision and Information Technology, CMVIT 2017 - Singapore, Singapore
Duration: 2017 Feb 172017 Feb 19

Other

Other2017 International Conference on Machine Vision and Information Technology, CMVIT 2017
CountrySingapore
CitySingapore
Period17/2/1717/2/19

Keywords

  • FPGA
  • high frame rate
  • KLT
  • localized processing
  • real-time
  • ultra-low delay

ASJC Scopus subject areas

  • Computer Science Applications
  • Signal Processing
  • Computer Vision and Pattern Recognition

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  • Cite this

    Hu, T., Wu, H., & Ikenaga, T. (2017). FPGA implementation of high frame rate and ultra-low delay tracking with local-search based block matching. In Proceedings - 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017 (pp. 93-98). [7878721] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CMVIT.2017.24