FPGA implementation of high frame rate and ultra-low delay tracking with local-search based block matching

Tingting Hu, Hong Wu, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

As more and more human-machine interactive applications call for higher frame rate and lower delay to get a better experience, there is an inevitable need for high frame rate and ultra-low delay image processing system. Current existing works based on vision chip target on video with simple patterns or simple shapes in order to get a higher speed, which is reasonable in the first trial of this new field. However, more complicated system is required for real-life applications. This paper proposes a KLT (Kanade-Lucas-Tomasi) based tracking system with high frame rate and ultra-low delay, implemented on FPGA board. And based on the framework of KLT, local maximum neighboring check, local-search based SAD (Sum of Absolute Difference) block matching and coordinate-addressed feature storage are proposed to localize the whole algorithm. In a broader framework, the whole system is made parallelized and pipelined in order to get a high throughput which can meet the high frame rate and ultra-low delay system's demand. Evaluation results show that the proposed hardware system can work at 784fps and 0.762ms delay with resolution of 640×480.

Original languageEnglish
Title of host publicationProceedings - 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages93-98
Number of pages6
ISBN (Electronic)9781509049936
DOIs
Publication statusPublished - 2017 Mar 14
Event2017 International Conference on Machine Vision and Information Technology, CMVIT 2017 - Singapore, Singapore
Duration: 2017 Feb 172017 Feb 19

Other

Other2017 International Conference on Machine Vision and Information Technology, CMVIT 2017
CountrySingapore
CitySingapore
Period17/2/1717/2/19

Fingerprint

Field programmable gate arrays (FPGA)
Image processing
Throughput
Hardware

Keywords

  • FPGA
  • high frame rate
  • KLT
  • localized processing
  • real-time
  • ultra-low delay

ASJC Scopus subject areas

  • Computer Science Applications
  • Signal Processing
  • Computer Vision and Pattern Recognition

Cite this

Hu, T., Wu, H., & Ikenaga, T. (2017). FPGA implementation of high frame rate and ultra-low delay tracking with local-search based block matching. In Proceedings - 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017 (pp. 93-98). [7878721] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CMVIT.2017.24

FPGA implementation of high frame rate and ultra-low delay tracking with local-search based block matching. / Hu, Tingting; Wu, Hong; Ikenaga, Takeshi.

Proceedings - 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 93-98 7878721.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hu, T, Wu, H & Ikenaga, T 2017, FPGA implementation of high frame rate and ultra-low delay tracking with local-search based block matching. in Proceedings - 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017., 7878721, Institute of Electrical and Electronics Engineers Inc., pp. 93-98, 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017, Singapore, Singapore, 17/2/17. https://doi.org/10.1109/CMVIT.2017.24
Hu T, Wu H, Ikenaga T. FPGA implementation of high frame rate and ultra-low delay tracking with local-search based block matching. In Proceedings - 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 93-98. 7878721 https://doi.org/10.1109/CMVIT.2017.24
Hu, Tingting ; Wu, Hong ; Ikenaga, Takeshi. / FPGA implementation of high frame rate and ultra-low delay tracking with local-search based block matching. Proceedings - 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 93-98
@inproceedings{a7d152be75d04fb88552f2fd39a62cf7,
title = "FPGA implementation of high frame rate and ultra-low delay tracking with local-search based block matching",
abstract = "As more and more human-machine interactive applications call for higher frame rate and lower delay to get a better experience, there is an inevitable need for high frame rate and ultra-low delay image processing system. Current existing works based on vision chip target on video with simple patterns or simple shapes in order to get a higher speed, which is reasonable in the first trial of this new field. However, more complicated system is required for real-life applications. This paper proposes a KLT (Kanade-Lucas-Tomasi) based tracking system with high frame rate and ultra-low delay, implemented on FPGA board. And based on the framework of KLT, local maximum neighboring check, local-search based SAD (Sum of Absolute Difference) block matching and coordinate-addressed feature storage are proposed to localize the whole algorithm. In a broader framework, the whole system is made parallelized and pipelined in order to get a high throughput which can meet the high frame rate and ultra-low delay system's demand. Evaluation results show that the proposed hardware system can work at 784fps and 0.762ms delay with resolution of 640×480.",
keywords = "FPGA, high frame rate, KLT, localized processing, real-time, ultra-low delay",
author = "Tingting Hu and Hong Wu and Takeshi Ikenaga",
year = "2017",
month = "3",
day = "14",
doi = "10.1109/CMVIT.2017.24",
language = "English",
pages = "93--98",
booktitle = "Proceedings - 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

TY - GEN

T1 - FPGA implementation of high frame rate and ultra-low delay tracking with local-search based block matching

AU - Hu, Tingting

AU - Wu, Hong

AU - Ikenaga, Takeshi

PY - 2017/3/14

Y1 - 2017/3/14

N2 - As more and more human-machine interactive applications call for higher frame rate and lower delay to get a better experience, there is an inevitable need for high frame rate and ultra-low delay image processing system. Current existing works based on vision chip target on video with simple patterns or simple shapes in order to get a higher speed, which is reasonable in the first trial of this new field. However, more complicated system is required for real-life applications. This paper proposes a KLT (Kanade-Lucas-Tomasi) based tracking system with high frame rate and ultra-low delay, implemented on FPGA board. And based on the framework of KLT, local maximum neighboring check, local-search based SAD (Sum of Absolute Difference) block matching and coordinate-addressed feature storage are proposed to localize the whole algorithm. In a broader framework, the whole system is made parallelized and pipelined in order to get a high throughput which can meet the high frame rate and ultra-low delay system's demand. Evaluation results show that the proposed hardware system can work at 784fps and 0.762ms delay with resolution of 640×480.

AB - As more and more human-machine interactive applications call for higher frame rate and lower delay to get a better experience, there is an inevitable need for high frame rate and ultra-low delay image processing system. Current existing works based on vision chip target on video with simple patterns or simple shapes in order to get a higher speed, which is reasonable in the first trial of this new field. However, more complicated system is required for real-life applications. This paper proposes a KLT (Kanade-Lucas-Tomasi) based tracking system with high frame rate and ultra-low delay, implemented on FPGA board. And based on the framework of KLT, local maximum neighboring check, local-search based SAD (Sum of Absolute Difference) block matching and coordinate-addressed feature storage are proposed to localize the whole algorithm. In a broader framework, the whole system is made parallelized and pipelined in order to get a high throughput which can meet the high frame rate and ultra-low delay system's demand. Evaluation results show that the proposed hardware system can work at 784fps and 0.762ms delay with resolution of 640×480.

KW - FPGA

KW - high frame rate

KW - KLT

KW - localized processing

KW - real-time

KW - ultra-low delay

UR - http://www.scopus.com/inward/record.url?scp=85017244869&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85017244869&partnerID=8YFLogxK

U2 - 10.1109/CMVIT.2017.24

DO - 10.1109/CMVIT.2017.24

M3 - Conference contribution

SP - 93

EP - 98

BT - Proceedings - 2017 International Conference on Machine Vision and Information Technology, CMVIT 2017

PB - Institute of Electrical and Electronics Engineers Inc.

ER -