FPGA implementation of high frame rate and ultra-low delay vision system with local and global parallel based matching

Tingting Hu, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

High frame rate and ultra-low delay image processing system plays an increasingly important role in human-machine interactive applications which call for a better experience. Current works based on vision chip target on video with simple patterns or simple shapes in order to get a higher speed, while a more complicated system is required for real-life applications. This paper proposes a BRIEF based matching system with high frame rate and ultra-low delay for specific object tracking, implemented on FPGA board. Local parallel and global pipeline based matching and 4-1-4 thread transformation are proposed for the implementation of this system. Local parallel and global pipeline based matching is proposed for high-speed matching. And 4-1-4 thread transformation is proposed to reduce the enormous resource cost caused by highly paralled and pipelined structure. In a broader framework, the proposed image processing system is made parallelized and pipelined for a high throughput which can meet the high frame rate and ultra-low delay system's demand. Evaluation results show that the proposed image processing core can work at 1306fps and 0.808ms delay with the resolution of 640×480. System using the image processing core and a camera with 784fps frame rate and 640×480 resolution is designed.

Original languageEnglish
Title of host publicationProceedings of the 15th IAPR International Conference on Machine Vision Applications, MVA 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages286-289
Number of pages4
ISBN (Electronic)9784901122160
DOIs
Publication statusPublished - 2017 Jul 19
Event15th IAPR International Conference on Machine Vision Applications, MVA 2017 - Nagoya, Japan
Duration: 2017 May 82017 May 12

Other

Other15th IAPR International Conference on Machine Vision Applications, MVA 2017
CountryJapan
CityNagoya
Period17/5/817/5/12

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Vision and Pattern Recognition

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    Hu, T., & Ikenaga, T. (2017). FPGA implementation of high frame rate and ultra-low delay vision system with local and global parallel based matching. In Proceedings of the 15th IAPR International Conference on Machine Vision Applications, MVA 2017 (pp. 286-289). [7986857] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/MVA.2017.7986857