Full-scale whole device EMC/MD simulation of Si nanowire transistor including source and drain regions by utilizing graphic processing units

Akito Suzuki, Takanobu Watanabe, Yoshinari Kamakura, Takefumi Kamioka

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    We have realized the full-scale whole device EMC/MD simulation including source and drain regions by utilizing graphic processing unit. The transfer characteristic of a gate-all-around nanowire Si MOSFET is simulated by reproducing the field effect of the surrounding gate electrode with spreading charged particles on the gate insulator layer. We have found an appreciable impact of the random dopant distribution (RDF) in source and drain regions on the drain current variability. Furthermore, the dynamic fluctuation of the drain current is found to be increase as the channel length decreases. The EMC/MD simulation powered by GPU is a useful method to investigate the dynamic fluctuation as well as the statistical device-to-device variability of nano-scale FETs.

    Original languageEnglish
    Title of host publicationInternational Conference on Simulation of Semiconductor Processes and Devices, SISPAD
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages357-360
    Number of pages4
    ISBN (Print)9781479952885
    DOIs
    Publication statusPublished - 2014 Oct 20
    Event2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014 - Yokohama
    Duration: 2014 Sep 92014 Sep 11

    Other

    Other2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014
    CityYokohama
    Period14/9/914/9/11

    Fingerprint

    MD Simulation
    Device Simulation
    Drain current
    Nanowires
    Electromagnetic compatibility
    Graphics Processing Unit
    Transistors
    Fluctuations
    MOSFET
    Insulator
    Charged particles
    Field effect transistors
    Electrode
    Doping (additives)
    Decrease
    Electrodes
    Graphics processing unit

    Keywords

    • ensemble Monte Carlo/molecular dynamics (EMC/MD)
    • Graphic Processing Unit (GPU)
    • random dopant fluctuation (RDF)
    • random telegraph noise (RTN)
    • Si nanowire Transistor

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Modelling and Simulation

    Cite this

    Suzuki, A., Watanabe, T., Kamakura, Y., & Kamioka, T. (2014). Full-scale whole device EMC/MD simulation of Si nanowire transistor including source and drain regions by utilizing graphic processing units. In International Conference on Simulation of Semiconductor Processes and Devices, SISPAD (pp. 357-360). [6931637] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SISPAD.2014.6931637

    Full-scale whole device EMC/MD simulation of Si nanowire transistor including source and drain regions by utilizing graphic processing units. / Suzuki, Akito; Watanabe, Takanobu; Kamakura, Yoshinari; Kamioka, Takefumi.

    International Conference on Simulation of Semiconductor Processes and Devices, SISPAD. Institute of Electrical and Electronics Engineers Inc., 2014. p. 357-360 6931637.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Suzuki, A, Watanabe, T, Kamakura, Y & Kamioka, T 2014, Full-scale whole device EMC/MD simulation of Si nanowire transistor including source and drain regions by utilizing graphic processing units. in International Conference on Simulation of Semiconductor Processes and Devices, SISPAD., 6931637, Institute of Electrical and Electronics Engineers Inc., pp. 357-360, 2014 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2014, Yokohama, 14/9/9. https://doi.org/10.1109/SISPAD.2014.6931637
    Suzuki A, Watanabe T, Kamakura Y, Kamioka T. Full-scale whole device EMC/MD simulation of Si nanowire transistor including source and drain regions by utilizing graphic processing units. In International Conference on Simulation of Semiconductor Processes and Devices, SISPAD. Institute of Electrical and Electronics Engineers Inc. 2014. p. 357-360. 6931637 https://doi.org/10.1109/SISPAD.2014.6931637
    Suzuki, Akito ; Watanabe, Takanobu ; Kamakura, Yoshinari ; Kamioka, Takefumi. / Full-scale whole device EMC/MD simulation of Si nanowire transistor including source and drain regions by utilizing graphic processing units. International Conference on Simulation of Semiconductor Processes and Devices, SISPAD. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 357-360
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