Makoto Taniguchi, Tsutomu Yoshihara, Michihiro Yamada, Kazuhiro Shimotori, Takao Nakano, Yoshimi Gamou

Research output: Contribution to journalArticle

10 Citations (Scopus)


A novel high-speed low-power 64K dynamic RAM with enough margin has been attained using a double polysilicon and 3- mu m process technologies. To obtain a low soft error rate below 1 multiplied by 10** minus **6 errors per device hour without sacrificing the high-speed and low-power operation, some novel approaches are proposed in the designs. Fully boosted circuits and the Hi-C cell structure with polysilicon bit line are designed to increase the margin of the single 5-v power supply 64K dynamic RAM. The fabricated device provides a typical access time of 90 ns and an operating power of 190 mw at 25 degree C. The design features of the automatic and self-refresh functions on the same chip are described. 11 refs.

Original languageEnglish
Pages (from-to)492-498
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Issue number5
Publication statusPublished - 1981 Oct
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'FULLY BOOSTED 64K DYNAMIC RAM WITH AUTOMATIC AND SELF-REFRESH.'. Together they form a unique fingerprint.

  • Cite this

    Taniguchi, M., Yoshihara, T., Yamada, M., Shimotori, K., Nakano, T., & Gamou, Y. (1981). FULLY BOOSTED 64K DYNAMIC RAM WITH AUTOMATIC AND SELF-REFRESH. IEEE Journal of Solid-State Circuits, SC-16(5), 492-498.