Fully-integrated novel high efficiency linear CMOS power amplifier for 5.8 GHz ETC applications

YongJu Suh, Jiangtao Sun, Koji Horie, Nobuyuki Itoh, Toshihiko Yoshimasu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

A fully integrated novel power amplifier (PA) using 130nm CMOS process is presented for Electric Toll Collection (ETC) applications. To obtain good efficiency and high linear gain performance, a novel cascode PA based on a class E PA has been designed, fabricated and fully measured. The proposed PA is a single-ended single-stage amplifier at an operating voltage of only 2 V. The power added efficiency (PAE) of the PA is as high as 42.6% with a gain of 11.4dB at P1dB of 13.4dBm. This CMOS PA includes all matching circuits and biasing circuits, and no external components are required.

Original languageEnglish
Title of host publicationAPMC 2009 - Asia Pacific Microwave Conference 2009
Pages365-368
Number of pages4
DOIs
Publication statusPublished - 2009
EventAsia Pacific Microwave Conference 2009, APMC 2009 - Singapore
Duration: 2009 Dec 72009 Dec 10

Other

OtherAsia Pacific Microwave Conference 2009, APMC 2009
CitySingapore
Period09/12/709/12/10

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Keywords

  • CMOS
  • Electric toll collection
  • High efficiency
  • Power amplifier

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Suh, Y., Sun, J., Horie, K., Itoh, N., & Yoshimasu, T. (2009). Fully-integrated novel high efficiency linear CMOS power amplifier for 5.8 GHz ETC applications. In APMC 2009 - Asia Pacific Microwave Conference 2009 (pp. 365-368). [5384529] https://doi.org/10.1109/APMC.2009.5384529