GAAS 1-KBIT STATIC RAM WITH A SHALLOW RECESSED-GATE STRUCTURE FET.

Satoshi Takano, Noriyuki Tanino, Tsutomu Yoshihara, Yasuo Mitsui, Kazuo Nishitani

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

A novel GaAs FET structure has been developed. In order to decrease the source resistance and gate capacitance a shallow n** plus implanted layer was formed between the gate and the source/drain region; then the gate region was slightly recessed. This FET has a high transconductance, low-source resistance, small gate capacitance, and small deviation of threshold voltage. It is suitable for high-speed GaAs LSIs. A 1-kbit static RAM has been designed and fabricated with this FET structure and an access time of 3. 8 ns with 38-mW power dissipation has been obtained.

Original languageEnglish
Pages (from-to)1135-1139
Number of pages5
JournalIEEE Transactions on Electron Devices
VolumeED-32
Issue number6
Publication statusPublished - 1985 Jun
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Physics and Astronomy (miscellaneous)

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    Takano, S., Tanino, N., Yoshihara, T., Mitsui, Y., & Nishitani, K. (1985). GAAS 1-KBIT STATIC RAM WITH A SHALLOW RECESSED-GATE STRUCTURE FET. IEEE Transactions on Electron Devices, ED-32(6), 1135-1139.