Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability

Masahide Inuishi, K. Mitsui, S. Kusunoki, H. Oda, K. Tsukamoto, Y. Akasaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

The authors present the gate capacitance characteristics of the gate/N/sup -/ overlap LDD (lightly doped drain) transistor. The gate capacitance was directly measured by a four-terminal method, using an LCR meter. The measured results for the overlap LDD were compared with those for the single drain and the LDD structure. It was demonstrated that the gate/drain capacitance for the overlap LDD is smaller than that for the single drain and as small as that for the LDD in spite of the large overlap length between the gate and the N/sup -/ region. This result was also confirmed by simulation, which indicates that the small gate/drain capacitance of the overlap LDD is due to the depletion of the N/sup -/ drain under the gate by the normal electric field from the gate and the lateral electric field at the drain.

Original languageEnglish
Title of host publicationInternational Electron Devices Meeting 1991, IEDM 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages371-374
Number of pages4
Volume1991-January
ISBN (Electronic)0780302435
DOIs
Publication statusPublished - 1991
Externally publishedYes
EventInternational Electron Devices Meeting, IEDM 1991 - Washington, United States
Duration: 1991 Dec 81991 Dec 11

Other

OtherInternational Electron Devices Meeting, IEDM 1991
CountryUnited States
CityWashington
Period91/12/891/12/11

Fingerprint

Transistors
Capacitance
transistors
capacitance
Electric fields
electric fields
depletion
simulation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics
  • Electronic, Optical and Magnetic Materials
  • Materials Chemistry

Cite this

Inuishi, M., Mitsui, K., Kusunoki, S., Oda, H., Tsukamoto, K., & Akasaka, Y. (1991). Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability. In International Electron Devices Meeting 1991, IEDM 1991 (Vol. 1991-January, pp. 371-374). [235376] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.1991.235376

Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability. / Inuishi, Masahide; Mitsui, K.; Kusunoki, S.; Oda, H.; Tsukamoto, K.; Akasaka, Y.

International Electron Devices Meeting 1991, IEDM 1991. Vol. 1991-January Institute of Electrical and Electronics Engineers Inc., 1991. p. 371-374 235376.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Inuishi, M, Mitsui, K, Kusunoki, S, Oda, H, Tsukamoto, K & Akasaka, Y 1991, Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability. in International Electron Devices Meeting 1991, IEDM 1991. vol. 1991-January, 235376, Institute of Electrical and Electronics Engineers Inc., pp. 371-374, International Electron Devices Meeting, IEDM 1991, Washington, United States, 91/12/8. https://doi.org/10.1109/IEDM.1991.235376
Inuishi M, Mitsui K, Kusunoki S, Oda H, Tsukamoto K, Akasaka Y. Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability. In International Electron Devices Meeting 1991, IEDM 1991. Vol. 1991-January. Institute of Electrical and Electronics Engineers Inc. 1991. p. 371-374. 235376 https://doi.org/10.1109/IEDM.1991.235376
Inuishi, Masahide ; Mitsui, K. ; Kusunoki, S. ; Oda, H. ; Tsukamoto, K. ; Akasaka, Y. / Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability. International Electron Devices Meeting 1991, IEDM 1991. Vol. 1991-January Institute of Electrical and Electronics Engineers Inc., 1991. pp. 371-374
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N2 - The authors present the gate capacitance characteristics of the gate/N/sup -/ overlap LDD (lightly doped drain) transistor. The gate capacitance was directly measured by a four-terminal method, using an LCR meter. The measured results for the overlap LDD were compared with those for the single drain and the LDD structure. It was demonstrated that the gate/drain capacitance for the overlap LDD is smaller than that for the single drain and as small as that for the LDD in spite of the large overlap length between the gate and the N/sup -/ region. This result was also confirmed by simulation, which indicates that the small gate/drain capacitance of the overlap LDD is due to the depletion of the N/sup -/ drain under the gate by the normal electric field from the gate and the lateral electric field at the drain.

AB - The authors present the gate capacitance characteristics of the gate/N/sup -/ overlap LDD (lightly doped drain) transistor. The gate capacitance was directly measured by a four-terminal method, using an LCR meter. The measured results for the overlap LDD were compared with those for the single drain and the LDD structure. It was demonstrated that the gate/drain capacitance for the overlap LDD is smaller than that for the single drain and as small as that for the LDD in spite of the large overlap length between the gate and the N/sup -/ region. This result was also confirmed by simulation, which indicates that the small gate/drain capacitance of the overlap LDD is due to the depletion of the N/sup -/ drain under the gate by the normal electric field from the gate and the lateral electric field at the drain.

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