Gate electrode engineering by control of grain growth for high performance and high reliable 0.18 μm dual gate CMOS

S. Shimizu, T. Kuroi, H. Sayama, A. Furukawa, Y. Nishida, Y. Inoue, M. Inuishi, T. Nishimura

Research output: Contribution to journalConference article

10 Citations (Scopus)

Abstract

Advanced gate electrode engineering is demonstrated to overcome the key issues of dual gate CMOS with thin gate oxide film. Using the small-grain-size polysilicon for the gate electrode, not only the suppression of gate depletion but also the stability of threshold voltage can be achieved as well as the improvement of the gate oxide integrity. Furthermore this successful implementation into 0.18 μm in CMOS is demonstrated with high performance and high reliability.

Original languageEnglish
Pages (from-to)107-108
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 1997 Jan 1
Externally publishedYes
EventProceedings of the 1997 Symposium on VLSI Technology - Kyoto, Jpn
Duration: 1997 Jun 101997 Jun 12

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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