Abstract
Permutation network plays an important role in the reconfigurable QC-LDPC decoder for most modern wireless communication systems with multiple code rates and various code lengths. This paper presents the generic permutation network (GPN) for the reconfigurable QC-LDPC decoder. Compared with conventional permutation networks, this proposal could break through the input number restriction, such as power of 2 and other limited number, and optimize the network for any application in demand. Moreover, the proposed scheme could greatly reduce the latency because of less stages and efficient control signal generating algorithm. In addition, the proposed network processes the nature of high parallelism which could enable several groups of data to be cyclically shifted simultaneously. The synthesis results using the 90 nm technology demonstrate that this architecture can be implemented with the gate count of 18.3k for WiMAX standard at the frequency of 600 MHz and 10.9k for WiFi standard at the frequency of 800 MHz.
| Original language | English |
|---|---|
| Pages (from-to) | 2551-2559 |
| Number of pages | 9 |
| Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| Volume | E93-A |
| Issue number | 12 |
| DOIs | |
| Publication status | Published - 2010 Dec |
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Keywords
- LDPC decoder
- Parallelism
- Permutation network
- Reconfigurable
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Computer Graphics and Computer-Aided Design
- Applied Mathematics
- Signal Processing
Cite this
Generic permutation network for QC-LDPC decoder. / Peng, Xiao; Zhao, Xiongxin; Chen, Zhixiang; Maehara, Fumiaki; Goto, Satoshi.
In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E93-A, No. 12, 12.2010, p. 2551-2559.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Generic permutation network for QC-LDPC decoder
AU - Peng, Xiao
AU - Zhao, Xiongxin
AU - Chen, Zhixiang
AU - Maehara, Fumiaki
AU - Goto, Satoshi
PY - 2010/12
Y1 - 2010/12
N2 - Permutation network plays an important role in the reconfigurable QC-LDPC decoder for most modern wireless communication systems with multiple code rates and various code lengths. This paper presents the generic permutation network (GPN) for the reconfigurable QC-LDPC decoder. Compared with conventional permutation networks, this proposal could break through the input number restriction, such as power of 2 and other limited number, and optimize the network for any application in demand. Moreover, the proposed scheme could greatly reduce the latency because of less stages and efficient control signal generating algorithm. In addition, the proposed network processes the nature of high parallelism which could enable several groups of data to be cyclically shifted simultaneously. The synthesis results using the 90 nm technology demonstrate that this architecture can be implemented with the gate count of 18.3k for WiMAX standard at the frequency of 600 MHz and 10.9k for WiFi standard at the frequency of 800 MHz.
AB - Permutation network plays an important role in the reconfigurable QC-LDPC decoder for most modern wireless communication systems with multiple code rates and various code lengths. This paper presents the generic permutation network (GPN) for the reconfigurable QC-LDPC decoder. Compared with conventional permutation networks, this proposal could break through the input number restriction, such as power of 2 and other limited number, and optimize the network for any application in demand. Moreover, the proposed scheme could greatly reduce the latency because of less stages and efficient control signal generating algorithm. In addition, the proposed network processes the nature of high parallelism which could enable several groups of data to be cyclically shifted simultaneously. The synthesis results using the 90 nm technology demonstrate that this architecture can be implemented with the gate count of 18.3k for WiMAX standard at the frequency of 600 MHz and 10.9k for WiFi standard at the frequency of 800 MHz.
KW - LDPC decoder
KW - Parallelism
KW - Permutation network
KW - Reconfigurable
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U2 - 10.1587/transfun.E93.A.2551
DO - 10.1587/transfun.E93.A.2551
M3 - Article
AN - SCOPUS:78650010106
VL - E93-A
SP - 2551
EP - 2559
JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
SN - 0916-8508
IS - 12
ER -