Global code scheduling technique using guarded PDG

Akira Koseki, Hideaki Komatsu, Yoshiaki Fukazawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    For instruction-level parallel machines, it is essential to extract parallel executable instructions from a program by code scheduling. In this paper, we propose a new code scheduling technique using an extension of PDG. This technique parallelizes non-numerical programs, producing better machine codes than these created by percolation scheduling.

    Original languageEnglish
    Title of host publicationIEEE International Conference on Algorithms and Architectures for Parallel Processing
    Place of PublicationPiscataway, NJ, United States
    PublisherIEEE
    Pages661-669
    Number of pages9
    Volume2
    Publication statusPublished - 1995
    EventProceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2) - Brisbane, Aust
    Duration: 1995 Apr 191995 Apr 21

    Other

    OtherProceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2)
    CityBrisbane, Aust
    Period95/4/1995/4/21

    Fingerprint

    Scheduling

    ASJC Scopus subject areas

    • Computer Science(all)
    • Engineering(all)

    Cite this

    Koseki, A., Komatsu, H., & Fukazawa, Y. (1995). Global code scheduling technique using guarded PDG. In IEEE International Conference on Algorithms and Architectures for Parallel Processing (Vol. 2, pp. 661-669). Piscataway, NJ, United States: IEEE.

    Global code scheduling technique using guarded PDG. / Koseki, Akira; Komatsu, Hideaki; Fukazawa, Yoshiaki.

    IEEE International Conference on Algorithms and Architectures for Parallel Processing. Vol. 2 Piscataway, NJ, United States : IEEE, 1995. p. 661-669.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Koseki, A, Komatsu, H & Fukazawa, Y 1995, Global code scheduling technique using guarded PDG. in IEEE International Conference on Algorithms and Architectures for Parallel Processing. vol. 2, IEEE, Piscataway, NJ, United States, pp. 661-669, Proceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2), Brisbane, Aust, 95/4/19.
    Koseki A, Komatsu H, Fukazawa Y. Global code scheduling technique using guarded PDG. In IEEE International Conference on Algorithms and Architectures for Parallel Processing. Vol. 2. Piscataway, NJ, United States: IEEE. 1995. p. 661-669
    Koseki, Akira ; Komatsu, Hideaki ; Fukazawa, Yoshiaki. / Global code scheduling technique using guarded PDG. IEEE International Conference on Algorithms and Architectures for Parallel Processing. Vol. 2 Piscataway, NJ, United States : IEEE, 1995. pp. 661-669
    @inproceedings{4a290d06a03e4607889b61e4b94fa3a0,
    title = "Global code scheduling technique using guarded PDG",
    abstract = "For instruction-level parallel machines, it is essential to extract parallel executable instructions from a program by code scheduling. In this paper, we propose a new code scheduling technique using an extension of PDG. This technique parallelizes non-numerical programs, producing better machine codes than these created by percolation scheduling.",
    author = "Akira Koseki and Hideaki Komatsu and Yoshiaki Fukazawa",
    year = "1995",
    language = "English",
    volume = "2",
    pages = "661--669",
    booktitle = "IEEE International Conference on Algorithms and Architectures for Parallel Processing",
    publisher = "IEEE",

    }

    TY - GEN

    T1 - Global code scheduling technique using guarded PDG

    AU - Koseki, Akira

    AU - Komatsu, Hideaki

    AU - Fukazawa, Yoshiaki

    PY - 1995

    Y1 - 1995

    N2 - For instruction-level parallel machines, it is essential to extract parallel executable instructions from a program by code scheduling. In this paper, we propose a new code scheduling technique using an extension of PDG. This technique parallelizes non-numerical programs, producing better machine codes than these created by percolation scheduling.

    AB - For instruction-level parallel machines, it is essential to extract parallel executable instructions from a program by code scheduling. In this paper, we propose a new code scheduling technique using an extension of PDG. This technique parallelizes non-numerical programs, producing better machine codes than these created by percolation scheduling.

    UR - http://www.scopus.com/inward/record.url?scp=0029231859&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=0029231859&partnerID=8YFLogxK

    M3 - Conference contribution

    AN - SCOPUS:0029231859

    VL - 2

    SP - 661

    EP - 669

    BT - IEEE International Conference on Algorithms and Architectures for Parallel Processing

    PB - IEEE

    CY - Piscataway, NJ, United States

    ER -