Global code scheduling technique using guarded PDG

Akira Koseki, Hideaki Komatsu, Yoshiaki Fukazawa

Research output: Contribution to conferencePaperpeer-review

Abstract

For instruction-level parallel machines, it is essential to extract parallel executable instructions from a program by code scheduling. In this paper, we propose a new code scheduling technique using an extension of PDG. This technique parallelizes non-numerical programs, producing better machine codes than these created by percolation scheduling.

Original languageEnglish
Pages661-669
Number of pages9
Publication statusPublished - 1995 Jan 1
EventProceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2) - Brisbane, Aust
Duration: 1995 Apr 191995 Apr 21

Other

OtherProceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2)
CityBrisbane, Aust
Period95/4/1995/4/21

ASJC Scopus subject areas

  • Computer Science(all)
  • Engineering(all)

Fingerprint Dive into the research topics of 'Global code scheduling technique using guarded PDG'. Together they form a unique fingerprint.

Cite this