Global code scheduling technique using guarded PDG

Akira Koseki, Hideaki Komatsu, Yoshiaki Fukazawa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    For instruction-level parallel machines, it is essential to extract parallel executable instructions from a program by code scheduling. In this paper, we propose a new code scheduling technique using an extension of PDG. This technique parallelizes non-numerical programs, producing better machine codes than these created by percolation scheduling.

    Original languageEnglish
    Title of host publicationIEEE International Conference on Algorithms and Architectures for Parallel Processing
    Place of PublicationPiscataway, NJ, United States
    PublisherIEEE
    Pages661-669
    Number of pages9
    Volume2
    Publication statusPublished - 1995
    EventProceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2) - Brisbane, Aust
    Duration: 1995 Apr 191995 Apr 21

    Other

    OtherProceedings of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing. Part 1 (of 2)
    CityBrisbane, Aust
    Period95/4/1995/4/21

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    ASJC Scopus subject areas

    • Computer Science(all)
    • Engineering(all)

    Cite this

    Koseki, A., Komatsu, H., & Fukazawa, Y. (1995). Global code scheduling technique using guarded PDG. In IEEE International Conference on Algorithms and Architectures for Parallel Processing (Vol. 2, pp. 661-669). IEEE.