Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system

Kazuhiro Ueda, Okura Shunsuke, Fukashi Morishita, Kazutami Arimoto, Leona Okamura, Tsutomu Yoshihara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    For low power consumption which makes more than doubles a battery life, the charge-recycling system by reuse the energy between the two or more CPUs and the task scheduling technique for high efficiency are proposed. In this architecture, CPUs are divided into upper and lower load groups, and electrical charges are shared among the stacked CPUs and a tank capacitor. To control divided loads, a high speed and efficient regulator are needed. The internal circuit voltage variation between upper and lower modules is solved by seven LDO regulators, boosting switched capacitor and the tank capacitor. As a result, the stable voltage can be supplied to each CPU, even if upper and lower loads are different or battery is used. The LDOs improve the margin of accumulation of tank capacitor or task schedule operation, and the power efficiency is raised further. The system can be on-chip without external large control circuit and inductor like switching regulator. The test chips were fabricated using 90nm standard CMOS technology. Although the power efficiency of the conventional system with a simple LDO is 44.4% at the maximum, that of the proposed charge-recycling system improves to 88.9%.

    Original languageEnglish
    Title of host publicationProceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC
    Pages105-108
    Number of pages4
    DOIs
    Publication statusPublished - 2012
    Event2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe
    Duration: 2012 Nov 122012 Nov 14

    Other

    Other2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
    CityKobe
    Period12/11/1212/11/14

    Fingerprint

    Program processors
    Recycling
    Capacitors
    Semiconductor materials
    Networks (circuits)
    Electric potential
    Electric power utilization
    Scheduling

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Ueda, K., Shunsuke, O., Morishita, F., Arimoto, K., Okamura, L., & Yoshihara, T. (2012). Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system. In Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC (pp. 105-108). [6522638] https://doi.org/10.1109/IPEC.2012.6522638

    Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system. / Ueda, Kazuhiro; Shunsuke, Okura; Morishita, Fukashi; Arimoto, Kazutami; Okamura, Leona; Yoshihara, Tsutomu.

    Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC. 2012. p. 105-108 6522638.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Ueda, K, Shunsuke, O, Morishita, F, Arimoto, K, Okamura, L & Yoshihara, T 2012, Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system. in Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC., 6522638, pp. 105-108, 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012, Kobe, 12/11/12. https://doi.org/10.1109/IPEC.2012.6522638
    Ueda K, Shunsuke O, Morishita F, Arimoto K, Okamura L, Yoshihara T. Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system. In Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC. 2012. p. 105-108. 6522638 https://doi.org/10.1109/IPEC.2012.6522638
    Ueda, Kazuhiro ; Shunsuke, Okura ; Morishita, Fukashi ; Arimoto, Kazutami ; Okamura, Leona ; Yoshihara, Tsutomu. / Green semiconductor technology with ultra-low power on-chip charge-recycling power circuit and system. Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC. 2012. pp. 105-108
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