A technology for delineating fine patterns in an experimental 16-Mb DRAM fabrication process using an i-line 10X reduction stepper is discussed. The main features of the technology are a lithography method called peripherally added resist lithography (PEARL), a recessed memory array technique, and an exposure field composition. The usefulness of the technology has been verified using an experimental 16-Mb DRAM with an advanced stacked capacitor (STC) cell.
|Title of host publication||Digest of Technical Papers - Symposium on VLSI Technology|
|Publisher||Publ by IEEE|
|Number of pages||2|
|Publication status||Published - 1988|
ASJC Scopus subject areas
- Electrical and Electronic Engineering