Half micron technology for an experimental 16 Mbit DRAM using I-line stepper.

Y. Kawamoto, S. Kimura, N. Hasegawa, A. Hiraiwa, T. Kure, T. Nishida, M. Aoki, H. Sunami, K. Itoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A technology for delineating fine patterns in an experimental 16-Mb DRAM fabrication process using an i-line 10X reduction stepper is discussed. The main features of the technology are a lithography method called peripherally added resist lithography (PEARL), a recessed memory array technique, and an exposure field composition. The usefulness of the technology has been verified using an experimental 16-Mb DRAM with an advanced stacked capacitor (STC) cell.

Original languageEnglish
Title of host publicationDigest of Technical Papers - Symposium on VLSI Technology
PublisherPubl by IEEE
Pages17-18
Number of pages2
Publication statusPublished - 1988
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • Cite this

    Kawamoto, Y., Kimura, S., Hasegawa, N., Hiraiwa, A., Kure, T., Nishida, T., Aoki, M., Sunami, H., & Itoh, K. (1988). Half micron technology for an experimental 16 Mbit DRAM using I-line stepper. In Digest of Technical Papers - Symposium on VLSI Technology (pp. 17-18). Publ by IEEE.