Half micron technology for an experimental 16 Mbit DRAM using I-line stepper.

Y. Kawamoto; S. Kimura; N. Hasegawa; A. Hiraiwa; T. Kure; T. Nishida; M. Aoki; H. Sunami; K. Itoh

Half micron technology for an experimental 16 Mbit DRAM using I-line stepper.

Y. Kawamoto^*, S. Kimura, N. Hasegawa, A. Hiraiwa, T. Kure, T. Nishida, M. Aoki, H. Sunami, K. Itoh

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

A technology for delineating fine patterns in an experimental 16-Mb DRAM fabrication process using an i-line 10X reduction stepper is discussed. The main features of the technology are a lithography method called peripherally added resist lithography (PEARL), a recessed memory array technique, and an exposure field composition. The usefulness of the technology has been verified using an experimental 16-Mb DRAM with an advanced stacked capacitor (STC) cell.

Original language	English
Title of host publication	Digest of Technical Papers - Symposium on VLSI Technology
Publisher	Publ by IEEE
Pages	17-18
Number of pages	2
Publication status	Published - 1988
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Half micron technology for an experimental 16 Mbit DRAM using I-line stepper.",

abstract = "A technology for delineating fine patterns in an experimental 16-Mb DRAM fabrication process using an i-line 10X reduction stepper is discussed. The main features of the technology are a lithography method called peripherally added resist lithography (PEARL), a recessed memory array technique, and an exposure field composition. The usefulness of the technology has been verified using an experimental 16-Mb DRAM with an advanced stacked capacitor (STC) cell.",

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AU - Kawamoto, Y.

AU - Kimura, S.

AU - Hasegawa, N.

AU - Hiraiwa, A.

AU - Kure, T.

AU - Nishida, T.

AU - Aoki, M.

AU - Sunami, H.

AU - Itoh, K.

PY - 1988

Y1 - 1988

N2 - A technology for delineating fine patterns in an experimental 16-Mb DRAM fabrication process using an i-line 10X reduction stepper is discussed. The main features of the technology are a lithography method called peripherally added resist lithography (PEARL), a recessed memory array technique, and an exposure field composition. The usefulness of the technology has been verified using an experimental 16-Mb DRAM with an advanced stacked capacitor (STC) cell.

AB - A technology for delineating fine patterns in an experimental 16-Mb DRAM fabrication process using an i-line 10X reduction stepper is discussed. The main features of the technology are a lithography method called peripherally added resist lithography (PEARL), a recessed memory array technique, and an exposure field composition. The usefulness of the technology has been verified using an experimental 16-Mb DRAM with an advanced stacked capacitor (STC) cell.

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M3 - Conference contribution

AN - SCOPUS:0024144385

SP - 17

EP - 18

BT - Digest of Technical Papers - Symposium on VLSI Technology

PB - Publ by IEEE

ER -

Half micron technology for an experimental 16 Mbit DRAM using I-line stepper.

Abstract

ASJC Scopus subject areas

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