Hardware architecture design of CABAC Codec for H.264/AVC

Lingfeng Li, Yang Song, Takeshi Ikenaga, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper presents a hardware architecture for Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec in H.264/AVC main profile. The similarities between encoding algorithm and decoding algorithm are explored to fulfill hardware reuse. Meanwhile, dynamic pipeline scheme is adopted, to speedup the throughput. The characteristics of CABAC algorithm are utilized to reduce pipeline latency. Proposed codec design is implemented under TSMC 0.18 μm technology. Results show that the equivalent gate counts is 33.2k when the maximum frequency is 230MHz. It is estimated that the proposed CABAC, codec can process the input binary symbol at 135Mb/s for encoding and 90Mb/s for decoding.

Original languageEnglish
Title of host publication2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
DOIs
Publication statusPublished - 2007
Event2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Hsinchu
Duration: 2007 Apr 252007 Apr 27

Other

Other2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
CityHsinchu
Period07/4/2507/4/27

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Li, L., Song, Y., Ikenaga, T., & Goto, S. (2007). Hardware architecture design of CABAC Codec for H.264/AVC. In 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers [4239449] https://doi.org/10.1109/VDAT.2007.373257