Hardware-assisted reliability enhancement for embedded multi-core virtualization design

Tsung Han Lin, Yuki Kinebuchi, Hiromasa Shimada, Hitoshi Mitake, Chen Yi Lee, Tatsuo Nakajima

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)

    Abstract

    In this paper, we propose a virtualization architecture for the multi-core embedded system to provide more sys- tem reliability and security while maintaining the same per- formance without introducing additional special hardware supports or having to implement complex protection mech- anism in the virtualization layer. Embedded virtualization design usually uses two kinds of approaches, traditional VMM and microkernel approaches, but both of them suffer from performance or engineering cost problems. To achieve better reliability and keep the virtualization layer design lightweighted, a common hardware component called local memory adopted in the multi-core embedded processors is used in this work. By taking this memory ar- chitecture's advantage, we can mitigate above-mentioned problems at once. We choose to re-map the virtualization layer's program called SPUMONE, which it runs all its guest systems in kernel space, on the local memory. By doing so, it can provide additional reliability and security for the entire system because the SPUMONE's design in a multi-core platform has each instance being installed on a separated processor core, which is different from the tradi- tional virtualization layer design, and therefore the content of each SPUMONE in the local memory is inaccessible to each others.

    Original languageEnglish
    Title of host publicationProceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011
    Pages101-105
    Number of pages5
    Volume2
    DOIs
    Publication statusPublished - 2011
    Event1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011 - Toyama
    Duration: 2011 Aug 282011 Aug 31

    Other

    Other1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011
    CityToyama
    Period11/8/2811/8/31

    Fingerprint

    Computer hardware
    Data storage equipment
    Memory architecture
    Embedded systems
    Virtualization
    Hardware
    Costs

    ASJC Scopus subject areas

    • Computer Science Applications
    • Computer Networks and Communications

    Cite this

    Lin, T. H., Kinebuchi, Y., Shimada, H., Mitake, H., Lee, C. Y., & Nakajima, T. (2011). Hardware-assisted reliability enhancement for embedded multi-core virtualization design. In Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011 (Vol. 2, pp. 101-105). [602999] https://doi.org/10.1109/RTCSA.2011.24

    Hardware-assisted reliability enhancement for embedded multi-core virtualization design. / Lin, Tsung Han; Kinebuchi, Yuki; Shimada, Hiromasa; Mitake, Hitoshi; Lee, Chen Yi; Nakajima, Tatsuo.

    Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. Vol. 2 2011. p. 101-105 602999.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Lin, TH, Kinebuchi, Y, Shimada, H, Mitake, H, Lee, CY & Nakajima, T 2011, Hardware-assisted reliability enhancement for embedded multi-core virtualization design. in Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. vol. 2, 602999, pp. 101-105, 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Co-located with the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2011, Toyama, 11/8/28. https://doi.org/10.1109/RTCSA.2011.24
    Lin TH, Kinebuchi Y, Shimada H, Mitake H, Lee CY, Nakajima T. Hardware-assisted reliability enhancement for embedded multi-core virtualization design. In Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. Vol. 2. 2011. p. 101-105. 602999 https://doi.org/10.1109/RTCSA.2011.24
    Lin, Tsung Han ; Kinebuchi, Yuki ; Shimada, Hiromasa ; Mitake, Hitoshi ; Lee, Chen Yi ; Nakajima, Tatsuo. / Hardware-assisted reliability enhancement for embedded multi-core virtualization design. Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011. Vol. 2 2011. pp. 101-105
    @inproceedings{82b02569fe804c86bcd80a20dd312466,
    title = "Hardware-assisted reliability enhancement for embedded multi-core virtualization design",
    abstract = "In this paper, we propose a virtualization architecture for the multi-core embedded system to provide more sys- tem reliability and security while maintaining the same per- formance without introducing additional special hardware supports or having to implement complex protection mech- anism in the virtualization layer. Embedded virtualization design usually uses two kinds of approaches, traditional VMM and microkernel approaches, but both of them suffer from performance or engineering cost problems. To achieve better reliability and keep the virtualization layer design lightweighted, a common hardware component called local memory adopted in the multi-core embedded processors is used in this work. By taking this memory ar- chitecture's advantage, we can mitigate above-mentioned problems at once. We choose to re-map the virtualization layer's program called SPUMONE, which it runs all its guest systems in kernel space, on the local memory. By doing so, it can provide additional reliability and security for the entire system because the SPUMONE's design in a multi-core platform has each instance being installed on a separated processor core, which is different from the tradi- tional virtualization layer design, and therefore the content of each SPUMONE in the local memory is inaccessible to each others.",
    author = "Lin, {Tsung Han} and Yuki Kinebuchi and Hiromasa Shimada and Hitoshi Mitake and Lee, {Chen Yi} and Tatsuo Nakajima",
    year = "2011",
    doi = "10.1109/RTCSA.2011.24",
    language = "English",
    isbn = "9780769545028",
    volume = "2",
    pages = "101--105",
    booktitle = "Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011",

    }

    TY - GEN

    T1 - Hardware-assisted reliability enhancement for embedded multi-core virtualization design

    AU - Lin, Tsung Han

    AU - Kinebuchi, Yuki

    AU - Shimada, Hiromasa

    AU - Mitake, Hitoshi

    AU - Lee, Chen Yi

    AU - Nakajima, Tatsuo

    PY - 2011

    Y1 - 2011

    N2 - In this paper, we propose a virtualization architecture for the multi-core embedded system to provide more sys- tem reliability and security while maintaining the same per- formance without introducing additional special hardware supports or having to implement complex protection mech- anism in the virtualization layer. Embedded virtualization design usually uses two kinds of approaches, traditional VMM and microkernel approaches, but both of them suffer from performance or engineering cost problems. To achieve better reliability and keep the virtualization layer design lightweighted, a common hardware component called local memory adopted in the multi-core embedded processors is used in this work. By taking this memory ar- chitecture's advantage, we can mitigate above-mentioned problems at once. We choose to re-map the virtualization layer's program called SPUMONE, which it runs all its guest systems in kernel space, on the local memory. By doing so, it can provide additional reliability and security for the entire system because the SPUMONE's design in a multi-core platform has each instance being installed on a separated processor core, which is different from the tradi- tional virtualization layer design, and therefore the content of each SPUMONE in the local memory is inaccessible to each others.

    AB - In this paper, we propose a virtualization architecture for the multi-core embedded system to provide more sys- tem reliability and security while maintaining the same per- formance without introducing additional special hardware supports or having to implement complex protection mech- anism in the virtualization layer. Embedded virtualization design usually uses two kinds of approaches, traditional VMM and microkernel approaches, but both of them suffer from performance or engineering cost problems. To achieve better reliability and keep the virtualization layer design lightweighted, a common hardware component called local memory adopted in the multi-core embedded processors is used in this work. By taking this memory ar- chitecture's advantage, we can mitigate above-mentioned problems at once. We choose to re-map the virtualization layer's program called SPUMONE, which it runs all its guest systems in kernel space, on the local memory. By doing so, it can provide additional reliability and security for the entire system because the SPUMONE's design in a multi-core platform has each instance being installed on a separated processor core, which is different from the tradi- tional virtualization layer design, and therefore the content of each SPUMONE in the local memory is inaccessible to each others.

    UR - http://www.scopus.com/inward/record.url?scp=84862957041&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84862957041&partnerID=8YFLogxK

    U2 - 10.1109/RTCSA.2011.24

    DO - 10.1109/RTCSA.2011.24

    M3 - Conference contribution

    SN - 9780769545028

    VL - 2

    SP - 101

    EP - 105

    BT - Proceedings - 1st International Workshop on Cyber-Physical Systems, Networks, and Applications, CPSNA 2011, Workshop Held During RTCSA 2011

    ER -