Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

Zhenyu Liu, Yiqing Huang, Yang Song, Satoshi Goto, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

One hardware efficient and high speed architecture for variableblock size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing theprocessing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1% hardware cost can be saved. With TSMC 0.18m CMOS 1P6M standard celllibrary, the maximum clock speed of this design is 227MHz in worstwork conditions (1.62V, 125°C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz.

Original languageEnglish
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Pages160-163
Number of pages4
DOIs
Publication statusPublished - 2007
Event17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore
Duration: 2007 Mar 112007 Mar 13

Other

Other17th Great Lakes Symposium on VLSI, GLSVLSI'07
CityStresa-Lago Maggiore
Period07/3/1107/3/13

Fingerprint

Motion estimation
Hardware
Adders
Clocks
Pipelines
Throughput
Networks (circuits)
Costs

Keywords

  • H.264
  • Variable block size motion estimation
  • VLSI

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Liu, Z., Huang, Y., Song, Y., Goto, S., & Ikenaga, T. (2007). Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI (pp. 160-163). [1228826] https://doi.org/10.1145/1228784.1228826

Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. / Liu, Zhenyu; Huang, Yiqing; Song, Yang; Goto, Satoshi; Ikenaga, Takeshi.

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2007. p. 160-163 1228826.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Liu, Z, Huang, Y, Song, Y, Goto, S & Ikenaga, T 2007, Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. in Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI., 1228826, pp. 160-163, 17th Great Lakes Symposium on VLSI, GLSVLSI'07, Stresa-Lago Maggiore, 07/3/11. https://doi.org/10.1145/1228784.1228826
Liu Z, Huang Y, Song Y, Goto S, Ikenaga T. Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2007. p. 160-163. 1228826 https://doi.org/10.1145/1228784.1228826
Liu, Zhenyu ; Huang, Yiqing ; Song, Yang ; Goto, Satoshi ; Ikenaga, Takeshi. / Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI. 2007. pp. 160-163
@inproceedings{78eb9bf8a713433a95c15f5cdb94ff56,
title = "Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC",
abstract = "One hardware efficient and high speed architecture for variableblock size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing theprocessing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1{\%} hardware cost can be saved. With TSMC 0.18m CMOS 1P6M standard celllibrary, the maximum clock speed of this design is 227MHz in worstwork conditions (1.62V, 125°C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz.",
keywords = "H.264, Variable block size motion estimation, VLSI",
author = "Zhenyu Liu and Yiqing Huang and Yang Song and Satoshi Goto and Takeshi Ikenaga",
year = "2007",
doi = "10.1145/1228784.1228826",
language = "English",
isbn = "159593605X",
pages = "160--163",
booktitle = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",

}

TY - GEN

T1 - Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

AU - Liu, Zhenyu

AU - Huang, Yiqing

AU - Song, Yang

AU - Goto, Satoshi

AU - Ikenaga, Takeshi

PY - 2007

Y1 - 2007

N2 - One hardware efficient and high speed architecture for variableblock size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing theprocessing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1% hardware cost can be saved. With TSMC 0.18m CMOS 1P6M standard celllibrary, the maximum clock speed of this design is 227MHz in worstwork conditions (1.62V, 125°C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz.

AB - One hardware efficient and high speed architecture for variableblock size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing theprocessing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1% hardware cost can be saved. With TSMC 0.18m CMOS 1P6M standard celllibrary, the maximum clock speed of this design is 227MHz in worstwork conditions (1.62V, 125°C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz.

KW - H.264

KW - Variable block size motion estimation

KW - VLSI

UR - http://www.scopus.com/inward/record.url?scp=34748923444&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34748923444&partnerID=8YFLogxK

U2 - 10.1145/1228784.1228826

DO - 10.1145/1228784.1228826

M3 - Conference contribution

AN - SCOPUS:34748923444

SN - 159593605X

SN - 9781595936059

SP - 160

EP - 163

BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

ER -