Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC

Zhenyu Liu, Yiqing Huang, Yang Song, Satoshi Goto, Takeshi Ikenaga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

Abstract

One hardware efficient and high speed architecture for variableblock size motion estimation in H.264 is presented in this paper. Through compressing the propagated data and optimizing theprocessing element and adder tree circuits in pipeline, this architecture gets more hardware efficient datapath logic. Compared with the original Propagate Partial SAD structure, 12.1% hardware cost can be saved. With TSMC 0.18m CMOS 1P6M standard celllibrary, the maximum clock speed of this design is 227MHz in worstwork conditions (1.62V, 125°C). With the 48x32 search range, the maximum throughput of our design is 147786 MB/S, which can be used in the real-time encoding of VGA resolution frame with 4 reference frames at 30Hz.

Original languageEnglish
Title of host publicationGLSVLSI'07
Subtitle of host publicationProceedings of the 2007 ACM Great Lakes Symposium on VLSI
Pages160-163
Number of pages4
DOIs
Publication statusPublished - 2007 Oct 1
Event17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore, Italy
Duration: 2007 Mar 112007 Mar 13

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Conference

Conference17th Great Lakes Symposium on VLSI, GLSVLSI'07
CountryItaly
CityStresa-Lago Maggiore
Period07/3/1107/3/13

Keywords

  • H.264
  • VLSI
  • Variable block size motion estimation

ASJC Scopus subject areas

  • Engineering(all)

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