TY - GEN
T1 - Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems
AU - Jozwik, Krzysztof
AU - Tomiyama, Hiroyuki
AU - Edahiro, Masato
AU - Honda, Shinya
AU - Takada, Hiroaki
PY - 2011
Y1 - 2011
N2 - In the field of embedded systems, where ever-growing demands for short time-to-market, low cost, low power, high performance and increased flexibility are prevalent, modern FPGAs (Field Programmable Gate Arrays) are gaining wider popularity in a variety of applications. Moreover, capability of DPR (Dynamic Partial Reconfiguration) found in some of these devices can further help in meeting these demands. With the increasing trend to integrate multiple functions into a single device, programming difficulty, well known for FPGAs, and the complexity of management of dynamically reconfigurable resources drive the need for an OS (Operating System). The OS would provide a well-defined computing model abstracting details and capacity of the underlying hardware. This paper familiarizes the readers with the topic of DPR, pointing out its advantages and limitations, and a related HW (hardware) multitasking computing model. Furthermore, it presents results of an ongoing research on an efficient hardware platform for HW multitasking and an accompanying OS extension which facilitates its programmability and serves as a base for fully fledged DPR embedded systems.
AB - In the field of embedded systems, where ever-growing demands for short time-to-market, low cost, low power, high performance and increased flexibility are prevalent, modern FPGAs (Field Programmable Gate Arrays) are gaining wider popularity in a variety of applications. Moreover, capability of DPR (Dynamic Partial Reconfiguration) found in some of these devices can further help in meeting these demands. With the increasing trend to integrate multiple functions into a single device, programming difficulty, well known for FPGAs, and the complexity of management of dynamically reconfigurable resources drive the need for an OS (Operating System). The OS would provide a well-defined computing model abstracting details and capacity of the underlying hardware. This paper familiarizes the readers with the topic of DPR, pointing out its advantages and limitations, and a related HW (hardware) multitasking computing model. Furthermore, it presents results of an ongoing research on an efficient hardware platform for HW multitasking and an accompanying OS extension which facilitates its programmability and serves as a base for fully fledged DPR embedded systems.
KW - Dynamic reconfiguration
KW - FPGA
KW - Runtime reconfiguration
UR - http://www.scopus.com/inward/record.url?scp=84857406191&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84857406191&partnerID=8YFLogxK
U2 - 10.1109/isocc.2011.6138678
DO - 10.1109/isocc.2011.6138678
M3 - Conference contribution
AN - SCOPUS:84857406191
SN - 9781457707100
T3 - 2011 International SoC Design Conference, ISOCC 2011
SP - 183
EP - 186
BT - 2011 International SoC Design Conference, ISOCC 2011
PB - IEEE Computer Society
T2 - 8th International SoC Design Conference 2011, ISOCC 2011
Y2 - 17 November 2011 through 18 November 2011
ER -