### Abstract

Variable block size (VBS) transform technique is adopted in Fidelity Range Extensions (FRExt) of H.264/AVC, in which 8 x 8/4 x 4 Hadamard transforms are adaptively employed during the fractional motion estimation. The hardwired VBS Hadamard transform unit is developed by authors and the following contributions are described in this literature: (1) Hardware reusing scheme is adopted in the architecture design; (2) In the light of the noise analysis, the intermediate data bit-truncation scheme is developed to reduce the hardware cost while maintaining its computational precision well; (3) With mathematical analysis, the bit-width of SATD value is reduced as compared to the intuitive implementation, therefore, the power and hardware cost are both optimized for the SATD generator implementation; (4) Hybrid 4:2/3:2 compressor based CSA tree is analyzed in the circuits design of SATD generator; and (5) Clock-gating technique is employed to reduce the power dissipation of 4x4 transform operation. With TSMC 0.18μm CMOS technology, experimental results reveal that 12.2-30.4% saving in hardware cost and 12.4-32.4% saving in power consumption are achieved by using our algorithms.

Original language | English |
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Title of host publication | Proceedings - International Conference on Image Processing, ICIP |

Publisher | IEEE Computer Society |

Pages | 2701-2704 |

Number of pages | 4 |

ISBN (Print) | 9781424456543 |

DOIs | |

Publication status | Published - 2009 |

Event | 2009 IEEE International Conference on Image Processing, ICIP 2009 - Cairo Duration: 2009 Nov 7 → 2009 Nov 10 |

### Other

Other | 2009 IEEE International Conference on Image Processing, ICIP 2009 |
---|---|

City | Cairo |

Period | 09/11/7 → 09/11/10 |

### Fingerprint

### Keywords

- FRExt
- H.264/AVC
- Hadamard transform
- Variable block size
- VLSI

### ASJC Scopus subject areas

- Software
- Computer Vision and Pattern Recognition
- Signal Processing

### Cite this

*Proceedings - International Conference on Image Processing, ICIP*(pp. 2701-2704). [5414107] IEEE Computer Society. https://doi.org/10.1109/ICIP.2009.5414107

**Hardware optimizations of variable block size hadamard transform for H.264/AVC FREXT.** / Liu, Zhenyu; Wang, Dongsheng; Ikenaga, Takeshi.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

*Proceedings - International Conference on Image Processing, ICIP.*, 5414107, IEEE Computer Society, pp. 2701-2704, 2009 IEEE International Conference on Image Processing, ICIP 2009, Cairo, 09/11/7. https://doi.org/10.1109/ICIP.2009.5414107

}

TY - GEN

T1 - Hardware optimizations of variable block size hadamard transform for H.264/AVC FREXT

AU - Liu, Zhenyu

AU - Wang, Dongsheng

AU - Ikenaga, Takeshi

PY - 2009

Y1 - 2009

N2 - Variable block size (VBS) transform technique is adopted in Fidelity Range Extensions (FRExt) of H.264/AVC, in which 8 x 8/4 x 4 Hadamard transforms are adaptively employed during the fractional motion estimation. The hardwired VBS Hadamard transform unit is developed by authors and the following contributions are described in this literature: (1) Hardware reusing scheme is adopted in the architecture design; (2) In the light of the noise analysis, the intermediate data bit-truncation scheme is developed to reduce the hardware cost while maintaining its computational precision well; (3) With mathematical analysis, the bit-width of SATD value is reduced as compared to the intuitive implementation, therefore, the power and hardware cost are both optimized for the SATD generator implementation; (4) Hybrid 4:2/3:2 compressor based CSA tree is analyzed in the circuits design of SATD generator; and (5) Clock-gating technique is employed to reduce the power dissipation of 4x4 transform operation. With TSMC 0.18μm CMOS technology, experimental results reveal that 12.2-30.4% saving in hardware cost and 12.4-32.4% saving in power consumption are achieved by using our algorithms.

AB - Variable block size (VBS) transform technique is adopted in Fidelity Range Extensions (FRExt) of H.264/AVC, in which 8 x 8/4 x 4 Hadamard transforms are adaptively employed during the fractional motion estimation. The hardwired VBS Hadamard transform unit is developed by authors and the following contributions are described in this literature: (1) Hardware reusing scheme is adopted in the architecture design; (2) In the light of the noise analysis, the intermediate data bit-truncation scheme is developed to reduce the hardware cost while maintaining its computational precision well; (3) With mathematical analysis, the bit-width of SATD value is reduced as compared to the intuitive implementation, therefore, the power and hardware cost are both optimized for the SATD generator implementation; (4) Hybrid 4:2/3:2 compressor based CSA tree is analyzed in the circuits design of SATD generator; and (5) Clock-gating technique is employed to reduce the power dissipation of 4x4 transform operation. With TSMC 0.18μm CMOS technology, experimental results reveal that 12.2-30.4% saving in hardware cost and 12.4-32.4% saving in power consumption are achieved by using our algorithms.

KW - FRExt

KW - H.264/AVC

KW - Hadamard transform

KW - Variable block size

KW - VLSI

UR - http://www.scopus.com/inward/record.url?scp=77951969640&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77951969640&partnerID=8YFLogxK

U2 - 10.1109/ICIP.2009.5414107

DO - 10.1109/ICIP.2009.5414107

M3 - Conference contribution

SN - 9781424456543

SP - 2701

EP - 2704

BT - Proceedings - International Conference on Image Processing, ICIP

PB - IEEE Computer Society

ER -