Hardware trojan detection and classification based on logic testing utilizing steady state learning

    Research output: Contribution to journalArticle

    Abstract

    Modern digital integrated circuits (ICs) are often designed and fabricated by third parties and tools, which can make IC design/ fabrication vulnerable to malicious modifications. The malicious circuits are generally referred to as hardware Trojans (HTs) and they are considered to be a serious security concern. In this paper, we propose a logic-Testing based HT detection and classification method utilizing steady state learning. We first observe that HTs are hidden while applying random test patterns in a short time but most of them can be activated in a very long-Term random circuit operation. Hence it is very natural that we learn steady signal-Transition states of every suspicious Trojan net in a netlist by performing short-Term random simulation. After that, we simulate or emulate the netlist in a very long time by giving random test patterns and obtain a set of signal-Transition states. By discovering correlation between them, our method detects HTs and finds out its behavior. HTs sometimes do not affect primary outputs but just leak information over side channels. Our method can be successfully applied to those types of HTs. Experimental results demonstrate that our method can successfully identify all the real Trojan nets to be Trojan nets and all the normal nets to be normal nets, while other existing logic-Testing HT detection methods cannot detect some of them. Moreover, our method can successfully detect HTs even if they are not really activated during long-Term random simulation. Our method also correctly guesses the HT behavior utilizing signal transition learning.

    Original languageEnglish
    Pages (from-to)2308-2319
    Number of pages12
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE101A
    Issue number12
    DOIs
    Publication statusPublished - 2018 Dec 1

    Fingerprint

    Hardware
    Logic
    Testing
    Transition State
    Integrated Circuits
    Digital integrated circuits
    Learning
    Hardware security
    Digital Circuits
    Networks (circuits)
    Circuit Design
    Guess
    Fabrication
    Simulation
    Output
    Experimental Results
    Demonstrate

    Keywords

    • Gate-level netlist
    • Hardware Trojans
    • Logic test
    • Signal transition
    • Steady state

    ASJC Scopus subject areas

    • Signal Processing
    • Computer Graphics and Computer-Aided Design
    • Electrical and Electronic Engineering
    • Applied Mathematics

    Cite this

    @article{544ebb4a4ebf4e6b8e324e625ebf1fe2,
    title = "Hardware trojan detection and classification based on logic testing utilizing steady state learning",
    abstract = "Modern digital integrated circuits (ICs) are often designed and fabricated by third parties and tools, which can make IC design/ fabrication vulnerable to malicious modifications. The malicious circuits are generally referred to as hardware Trojans (HTs) and they are considered to be a serious security concern. In this paper, we propose a logic-Testing based HT detection and classification method utilizing steady state learning. We first observe that HTs are hidden while applying random test patterns in a short time but most of them can be activated in a very long-Term random circuit operation. Hence it is very natural that we learn steady signal-Transition states of every suspicious Trojan net in a netlist by performing short-Term random simulation. After that, we simulate or emulate the netlist in a very long time by giving random test patterns and obtain a set of signal-Transition states. By discovering correlation between them, our method detects HTs and finds out its behavior. HTs sometimes do not affect primary outputs but just leak information over side channels. Our method can be successfully applied to those types of HTs. Experimental results demonstrate that our method can successfully identify all the real Trojan nets to be Trojan nets and all the normal nets to be normal nets, while other existing logic-Testing HT detection methods cannot detect some of them. Moreover, our method can successfully detect HTs even if they are not really activated during long-Term random simulation. Our method also correctly guesses the HT behavior utilizing signal transition learning.",
    keywords = "Gate-level netlist, Hardware Trojans, Logic test, Signal transition, Steady state",
    author = "Masaru Oya and Masao Yanagisawa and Nozomu Togawa",
    year = "2018",
    month = "12",
    day = "1",
    doi = "10.1587/transfun.E101.A.2308",
    language = "English",
    volume = "E101A",
    pages = "2308--2319",
    journal = "IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences",
    issn = "0916-8508",
    publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
    number = "12",

    }

    TY - JOUR

    T1 - Hardware trojan detection and classification based on logic testing utilizing steady state learning

    AU - Oya, Masaru

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

    PY - 2018/12/1

    Y1 - 2018/12/1

    N2 - Modern digital integrated circuits (ICs) are often designed and fabricated by third parties and tools, which can make IC design/ fabrication vulnerable to malicious modifications. The malicious circuits are generally referred to as hardware Trojans (HTs) and they are considered to be a serious security concern. In this paper, we propose a logic-Testing based HT detection and classification method utilizing steady state learning. We first observe that HTs are hidden while applying random test patterns in a short time but most of them can be activated in a very long-Term random circuit operation. Hence it is very natural that we learn steady signal-Transition states of every suspicious Trojan net in a netlist by performing short-Term random simulation. After that, we simulate or emulate the netlist in a very long time by giving random test patterns and obtain a set of signal-Transition states. By discovering correlation between them, our method detects HTs and finds out its behavior. HTs sometimes do not affect primary outputs but just leak information over side channels. Our method can be successfully applied to those types of HTs. Experimental results demonstrate that our method can successfully identify all the real Trojan nets to be Trojan nets and all the normal nets to be normal nets, while other existing logic-Testing HT detection methods cannot detect some of them. Moreover, our method can successfully detect HTs even if they are not really activated during long-Term random simulation. Our method also correctly guesses the HT behavior utilizing signal transition learning.

    AB - Modern digital integrated circuits (ICs) are often designed and fabricated by third parties and tools, which can make IC design/ fabrication vulnerable to malicious modifications. The malicious circuits are generally referred to as hardware Trojans (HTs) and they are considered to be a serious security concern. In this paper, we propose a logic-Testing based HT detection and classification method utilizing steady state learning. We first observe that HTs are hidden while applying random test patterns in a short time but most of them can be activated in a very long-Term random circuit operation. Hence it is very natural that we learn steady signal-Transition states of every suspicious Trojan net in a netlist by performing short-Term random simulation. After that, we simulate or emulate the netlist in a very long time by giving random test patterns and obtain a set of signal-Transition states. By discovering correlation between them, our method detects HTs and finds out its behavior. HTs sometimes do not affect primary outputs but just leak information over side channels. Our method can be successfully applied to those types of HTs. Experimental results demonstrate that our method can successfully identify all the real Trojan nets to be Trojan nets and all the normal nets to be normal nets, while other existing logic-Testing HT detection methods cannot detect some of them. Moreover, our method can successfully detect HTs even if they are not really activated during long-Term random simulation. Our method also correctly guesses the HT behavior utilizing signal transition learning.

    KW - Gate-level netlist

    KW - Hardware Trojans

    KW - Logic test

    KW - Signal transition

    KW - Steady state

    UR - http://www.scopus.com/inward/record.url?scp=85057437910&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=85057437910&partnerID=8YFLogxK

    U2 - 10.1587/transfun.E101.A.2308

    DO - 10.1587/transfun.E101.A.2308

    M3 - Article

    AN - SCOPUS:85057437910

    VL - E101A

    SP - 2308

    EP - 2319

    JO - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    JF - IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

    SN - 0916-8508

    IS - 12

    ER -