Hardware Trojans classification for gate-level netlists using multi-layer neural networks

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    19 Citations (Scopus)

    Abstract

    Recently, due to the increase of outsourcing in IC design and manufacturing, it has been reported that malicious third-party IC vendors often insert hardware Trojans into their products. Especially in IC design step, it is strongly required to detect hardware Trojans because malicious third-party vendors can easily insert hardware Trojans in their products. In this paper, we propose a machine-learning-based hardware-Trojan detection method for gate-level netlists using multi-layer neural networks. First, we extract 11 Trojan-net feature values for each net in a netlist. After that, we classify the nets in an unknown netlist into a set of Trojan nets and that of normal nets using multi-layer neural networks. We obtained at most 100% true positive rate with our proposed method.

    Original languageEnglish
    Title of host publication2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages227-232
    Number of pages6
    ISBN (Electronic)9781538603512
    DOIs
    Publication statusPublished - 2017 Sep 19
    Event23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017 - Thessaloniki, Greece
    Duration: 2017 Jul 32017 Jul 5

    Other

    Other23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017
    CountryGreece
    CityThessaloniki
    Period17/7/317/7/5

    Fingerprint

    Multilayer neural networks
    Hardware
    Outsourcing
    Learning systems
    Integrated circuit design

    Keywords

    • Gate-level netlist
    • Hardware Trojan
    • Machine learning
    • Multi-layer
    • Neural network

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality
    • Computer Networks and Communications
    • Hardware and Architecture
    • Control and Systems Engineering

    Cite this

    Hasegawa, K., Yanagisawa, M., & Togawa, N. (2017). Hardware Trojans classification for gate-level netlists using multi-layer neural networks. In 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017 (pp. 227-232). [8046227] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IOLTS.2017.8046227

    Hardware Trojans classification for gate-level netlists using multi-layer neural networks. / Hasegawa, Kento; Yanagisawa, Masao; Togawa, Nozomu.

    2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 227-232 8046227.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Hasegawa, K, Yanagisawa, M & Togawa, N 2017, Hardware Trojans classification for gate-level netlists using multi-layer neural networks. in 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017., 8046227, Institute of Electrical and Electronics Engineers Inc., pp. 227-232, 23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017, Thessaloniki, Greece, 17/7/3. https://doi.org/10.1109/IOLTS.2017.8046227
    Hasegawa K, Yanagisawa M, Togawa N. Hardware Trojans classification for gate-level netlists using multi-layer neural networks. In 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 227-232. 8046227 https://doi.org/10.1109/IOLTS.2017.8046227
    Hasegawa, Kento ; Yanagisawa, Masao ; Togawa, Nozomu. / Hardware Trojans classification for gate-level netlists using multi-layer neural networks. 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design, IOLTS 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 227-232
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