Hardware/software codesign method for a general purpose reconfigurable co-processor

Shinji Kimura, Mitsuteru Yukishita, Yasufumi Itou, Akira Nagoya, Makoto Hirao, Katumasa Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGA's, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via the DMA based memory sharing. We also show cooperation examples and the effectiveness of our approach for the fast execution of user processes.

Original languageEnglish
Title of host publicationHardware/Software Codesign - Proceedings of the International Workshop
Editors Anon
Pages147-151
Number of pages5
Publication statusPublished - 1997
Externally publishedYes
EventProceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97 - Braunschweig, Ger
Duration: 1997 Mar 241997 Mar 26

Other

OtherProceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97
CityBraunschweig, Ger
Period97/3/2497/3/26

Fingerprint

Computer systems
System buses
Dynamic mechanical analysis
Field programmable gate arrays (FPGA)
Hardware
Data storage equipment
Coprocessor
Hardware-software codesign

ASJC Scopus subject areas

  • Hardware and Architecture

Cite this

Kimura, S., Yukishita, M., Itou, Y., Nagoya, A., Hirao, M., & Watanabe, K. (1997). Hardware/software codesign method for a general purpose reconfigurable co-processor. In Anon (Ed.), Hardware/Software Codesign - Proceedings of the International Workshop (pp. 147-151)

Hardware/software codesign method for a general purpose reconfigurable co-processor. / Kimura, Shinji; Yukishita, Mitsuteru; Itou, Yasufumi; Nagoya, Akira; Hirao, Makoto; Watanabe, Katumasa.

Hardware/Software Codesign - Proceedings of the International Workshop. ed. / Anon. 1997. p. 147-151.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kimura, S, Yukishita, M, Itou, Y, Nagoya, A, Hirao, M & Watanabe, K 1997, Hardware/software codesign method for a general purpose reconfigurable co-processor. in Anon (ed.), Hardware/Software Codesign - Proceedings of the International Workshop. pp. 147-151, Proceedings of the 1997 5th International Workshop on Hardware/Software Codesign, CODES/CASHE'97, Braunschweig, Ger, 97/3/24.
Kimura S, Yukishita M, Itou Y, Nagoya A, Hirao M, Watanabe K. Hardware/software codesign method for a general purpose reconfigurable co-processor. In Anon, editor, Hardware/Software Codesign - Proceedings of the International Workshop. 1997. p. 147-151
Kimura, Shinji ; Yukishita, Mitsuteru ; Itou, Yasufumi ; Nagoya, Akira ; Hirao, Makoto ; Watanabe, Katumasa. / Hardware/software codesign method for a general purpose reconfigurable co-processor. Hardware/Software Codesign - Proceedings of the International Workshop. editor / Anon. 1997. pp. 147-151
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