Abstract
A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb System-in-Silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 $\mu\hbox{m}$ CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 $\hbox{mm}^{2}$ die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.
| Original language | English |
|---|---|
| Article number | 4768914 |
| Pages (from-to) | 594-608 |
| Number of pages | 15 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 44 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2009 Feb |
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Keywords
- H264/AVC
- Hardwired encoder
- Very large-scale integration (VLSI) architecture
- Video coding
- Video signal processing
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
HDTV1080p H.264/AVC encoder chip design and performance analysis. / Liu, Zhenyu; Song, Yang; Shao, Ming; Li, Shen; Li, Lingfeng; Ishiwata, Shunichi; Nakagawa, Masaki; Goto, Satoshi; Ikenaga, Takeshi.
In: IEEE Journal of Solid-State Circuits, Vol. 44, No. 2, 4768914, 02.2009, p. 594-608.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - HDTV1080p H.264/AVC encoder chip design and performance analysis
AU - Liu, Zhenyu
AU - Song, Yang
AU - Shao, Ming
AU - Li, Shen
AU - Li, Lingfeng
AU - Ishiwata, Shunichi
AU - Nakagawa, Masaki
AU - Goto, Satoshi
AU - Ikenaga, Takeshi
PY - 2009/2
Y1 - 2009/2
N2 - A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb System-in-Silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 $\mu\hbox{m}$ CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 $\hbox{mm}^{2}$ die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.
AB - A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb System-in-Silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 $\mu\hbox{m}$ CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 $\hbox{mm}^{2}$ die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.
KW - H264/AVC
KW - Hardwired encoder
KW - Very large-scale integration (VLSI) architecture
KW - Video coding
KW - Video signal processing
UR - http://www.scopus.com/inward/record.url?scp=59349121022&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=59349121022&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2008.2010797
DO - 10.1109/JSSC.2008.2010797
M3 - Article
AN - SCOPUS:59349121022
VL - 44
SP - 594
EP - 608
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 2
M1 - 4768914
ER -