HDTV1080p H.264/AVC encoder chip design and performance analysis

Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, Shunichi Ishiwata, Masaki Nakagawa, Satoshi Goto, Takeshi Ikenaga

Research output: Contribution to journalArticle

67 Citations (Scopus)

Abstract

A H.264/AVC baseline-profile real-time encoder for HDTV-1080p at 30 fps is proposed in this paper. On the basis of the specifications and algorithm optimizations, the dedicated hardware engines and one 32-bit Media embedded Processor (MeP) equipped with hardware extensions are mapped into the three-stage macroblock pipelining system architecture. This paper describes the design considerations for chief components, including high throughput integer motion estimation, data reusing fractional motion estimation, and hardware friendly mode reduction for intra prediction. The 11.5 Gbps 64 Mb System-in-Silicon DRAM is embedded to alleviate the external memory bandwidth. Using TSMC one-poly six-metal 0.18 $\mu\hbox{m}$ CMOS technology, the prototype chip is implemented with 1140 k logic gates and 108.3 KB internal SRAM. The SoC core occupies 27.1 $\hbox{mm}^{2}$ die area and consumes 1.41 W at 200 MHz execution speed in typical work conditions.

Original languageEnglish
Article number4768914
Pages (from-to)594-608
Number of pages15
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number2
DOIs
Publication statusPublished - 2009 Feb 1

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Keywords

  • H264/AVC
  • Hardwired encoder
  • Very large-scale integration (VLSI) architecture
  • Video coding
  • Video signal processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Liu, Z., Song, Y., Shao, M., Li, S., Li, L., Ishiwata, S., Nakagawa, M., Goto, S., & Ikenaga, T. (2009). HDTV1080p H.264/AVC encoder chip design and performance analysis. IEEE Journal of Solid-State Circuits, 44(2), 594-608. [4768914]. https://doi.org/10.1109/JSSC.2008.2010797