Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding

Hiroaki Shikano*, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

16 Citations (Scopus)


This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.

Original languageEnglish
Pages (from-to)902-908
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Issue number4
Publication statusPublished - 2008 Jan


  • AAC encoding
  • Accelerator
  • Dynamically reconfigurable processor
  • Heterogeneous multi-core
  • Parallel processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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