Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding

Hiroaki Shikano; Masaki Ito; Masafumi Onouchi; Takashi Todaka; Takanobu Tsunoda; Tomoyuki Kodama; Kunio Uchiyama; Toshihiko Odaka; Tatsuya Kamei; Ei Nagahama; Manabu Kusaoke; Yusuke Nitta; Yasutaka Wada; Keiji Kimura; Hironori Kasahara

doi:10.1109/JSSC.2008.917531

Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding

Hiroaki Shikano^*, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

^*Corresponding author for this work

School of Fundamental Science and Engineering

Research output: Contribution to journal › Article › peer-review

16 Citations (Scopus)

Abstract

This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.

Original language	English
Pages (from-to)	902-908
Number of pages	7
Journal	IEEE Journal of Solid-State Circuits
Volume	43
Issue number	4
DOIs	https://doi.org/10.1109/JSSC.2008.917531
Publication status	Published - 2008 Jan

Keywords

AAC encoding
Accelerator
Dynamically reconfigurable processor
Heterogeneous multi-core
Parallel processing

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/JSSC.2008.917531

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Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding. / Shikano, Hiroaki; Ito, Masaki; Onouchi, Masafumi; Todaka, Takashi; Tsunoda, Takanobu; Kodama, Tomoyuki; Uchiyama, Kunio; Odaka, Toshihiko; Kamei, Tatsuya; Nagahama, Ei; Kusaoke, Manabu; Nitta, Yusuke; Wada, Yasutaka; Kimura, Keiji ; Kasahara, Hironori.

In: IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, 01.2008, p. 902-908.

Research output: Contribution to journal › Article › peer-review

Shikano, Hiroaki ; Ito, Masaki ; Onouchi, Masafumi ; Todaka, Takashi ; Tsunoda, Takanobu ; Kodama, Tomoyuki ; Uchiyama, Kunio ; Odaka, Toshihiko ; Kamei, Tatsuya ; Nagahama, Ei ; Kusaoke, Manabu ; Nitta, Yusuke ; Wada, Yasutaka ; Kimura, Keiji ; Kasahara, Hironori. / Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding. In: IEEE Journal of Solid-State Circuits. 2008 ; Vol. 43, No. 4. pp. 902-908.

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abstract = "This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.",

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note = "Funding Information: Manuscript received September 8, 2007; revised December 3, 2007. Part of this work was supported by NEDO Advanced Heterogeneous Multiprocessor. H. Shikano, M. Ito, M. Onouchi, T. Todaka, T. Tsunoda, T. Kodama, K. Uchiyama, and T. Odaka are with Hitachi, Ltd., Tokyo 185-8601, Japan (e-mail: hiroaki.shikano.gm@hitachi.com). T. Kamei, E. Nagahama, M. Kusaoke, and Y. Nitta are with Renesas Technology Corporation, Tokyo 187-8588, Japan. H. Shikano, Y. Wada, K. Kimura, and H. Kasahara are with the Department of Computer Science, Waseda University, Tokyo 169-8555, Japan. Digital Object Identifier 10.1109/JSSC.2008.917531",

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AU - Tsunoda, Takanobu

AU - Kodama, Tomoyuki

AU - Uchiyama, Kunio

AU - Odaka, Toshihiko

AU - Kamei, Tatsuya

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AU - Kusaoke, Manabu

AU - Nitta, Yusuke

AU - Wada, Yasutaka

AU - Kimura, Keiji

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Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding

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Keywords

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