Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding

Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    Research output: Contribution to journal › Article

    15 Citations (Scopus)

    Abstract

    This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.

    Original languageEnglish
    Pages (from-to)902-908
    Number of pages7
    JournalIEEE Journal of Solid-State Circuits
    Volume43
    Issue number4
    DOIs
    Publication statusPublished - 2008 Jan

    Fingerprint

    Program processors
    Particle accelerators
    Memory architecture
    Computer programming
    Embedded systems
    Electric power utilization

    Keywords

    • AAC encoding
    • Accelerator
    • Dynamically reconfigurable processor
    • Heterogeneous multi-core
    • Parallel processing

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding. / Shikano, Hiroaki; Ito, Masaki; Onouchi, Masafumi; Todaka, Takashi; Tsunoda, Takanobu; Kodama, Tomoyuki; Uchiyama, Kunio; Odaka, Toshihiko; Kamei, Tatsuya; Nagahama, Ei; Kusaoke, Manabu; Nitta, Yusuke; Wada, Yasutaka; Kimura, Keiji; Kasahara, Hironori.

    In: IEEE Journal of Solid-State Circuits, Vol. 43, No. 4, 01.2008, p. 902-908.

    Research output: Contribution to journal › Article

    Shikano, H, Ito, M, Onouchi, M, Todaka, T, Tsunoda, T, Kodama, T, Uchiyama, K, Odaka, T, Kamei, T, Nagahama, E, Kusaoke, M, Nitta, Y, Wada, Y, Kimura, K & Kasahara, H 2008, 'Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding', IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 902-908. https://doi.org/10.1109/JSSC.2008.917531
    Shikano H, Ito M, Onouchi M, Todaka T, Tsunoda T, Kodama T et al. Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding. IEEE Journal of Solid-State Circuits. 2008 Jan;43(4):902-908. https://doi.org/10.1109/JSSC.2008.917531
    Shikano, Hiroaki ; Ito, Masaki ; Onouchi, Masafumi ; Todaka, Takashi ; Tsunoda, Takanobu ; Kodama, Tomoyuki ; Uchiyama, Kunio ; Odaka, Toshihiko ; Kamei, Tatsuya ; Nagahama, Ei ; Kusaoke, Manabu ; Nitta, Yusuke ; Wada, Yasutaka ; Kimura, Keiji ; Kasahara, Hironori. / Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding. In: IEEE Journal of Solid-State Circuits. 2008 ; Vol. 43, No. 4. pp. 902-908.
    @article{7a1cd596aede4fcc914a0294197402b4,
    title = "Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding",
    abstract = "This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.",
    keywords = "AAC encoding, Accelerator, Dynamically reconfigurable processor, Heterogeneous multi-core, Parallel processing",
    author = "Hiroaki Shikano and Masaki Ito and Masafumi Onouchi and Takashi Todaka and Takanobu Tsunoda and Tomoyuki Kodama and Kunio Uchiyama and Toshihiko Odaka and Tatsuya Kamei and Ei Nagahama and Manabu Kusaoke and Yusuke Nitta and Yasutaka Wada and Keiji Kimura and Hironori Kasahara",
    year = "2008",
    month = "1",
    doi = "10.1109/JSSC.2008.917531",
    language = "English",
    volume = "43",
    pages = "902--908",
    journal = "IEEE Journal of Solid-State Circuits",
    issn = "0018-9200",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",
    number = "4",

    }

    TY - JOUR

    T1 - Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding

    AU - Shikano, Hiroaki

    AU - Ito, Masaki

    AU - Onouchi, Masafumi

    AU - Todaka, Takashi

    AU - Tsunoda, Takanobu

    AU - Kodama, Tomoyuki

    AU - Uchiyama, Kunio

    AU - Odaka, Toshihiko

    AU - Kamei, Tatsuya

    AU - Nagahama, Ei

    AU - Kusaoke, Manabu

    AU - Nitta, Yusuke

    AU - Wada, Yasutaka

    AU - Kimura, Keiji

    AU - Kasahara, Hironori

    PY - 2008/1

    Y1 - 2008/1

    N2 - This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.

    AB - This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.

    KW - AAC encoding

    KW - Accelerator

    KW - Dynamically reconfigurable processor

    KW - Heterogeneous multi-core

    KW - Parallel processing

    UR - http://www.scopus.com/inward/record.url?scp=41549114584&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=41549114584&partnerID=8YFLogxK

    U2 - 10.1109/JSSC.2008.917531

    DO - 10.1109/JSSC.2008.917531

    M3 - Article

    AN - SCOPUS:41549114584

    VL - 43

    SP - 902

    EP - 908

    JO - IEEE Journal of Solid-State Circuits

    JF - IEEE Journal of Solid-State Circuits

    SN - 0018-9200

    IS - 4

    ER -

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