Heterogeneous multicore processor technologies for embedded systems

Kunio Uchiyama, Fumio Arakawa, Hironori Kasahara, Tohru Nojiri, Hideyuki Noda, Yasuhiro Tawara, Akio Idehara, Kenichi Iwata, Hiroaki Shikano

    Research output: Book/ReportBook

    5 Citations (Scopus)

    Abstract

    To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems; Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs; Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications.

    Original languageEnglish
    PublisherSpringer New York
    Number of pages224
    ISBN (Print)9781461402848, 1461402832, 9781461402831
    DOIs
    Publication statusPublished - 2012 Oct 1

    Fingerprint

    Embedded systems
    Program processors
    Computer operating systems
    Application programs
    Computer hardware
    Hardware
    System-on-chip

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Uchiyama, K., Arakawa, F., Kasahara, H., Nojiri, T., Noda, H., Tawara, Y., ... Shikano, H. (2012). Heterogeneous multicore processor technologies for embedded systems. Springer New York. https://doi.org/10.1007/978-1-4614-0284-8

    Heterogeneous multicore processor technologies for embedded systems. / Uchiyama, Kunio; Arakawa, Fumio; Kasahara, Hironori; Nojiri, Tohru; Noda, Hideyuki; Tawara, Yasuhiro; Idehara, Akio; Iwata, Kenichi; Shikano, Hiroaki.

    Springer New York, 2012. 224 p.

    Research output: Book/ReportBook

    Uchiyama, K, Arakawa, F, Kasahara, H, Nojiri, T, Noda, H, Tawara, Y, Idehara, A, Iwata, K & Shikano, H 2012, Heterogeneous multicore processor technologies for embedded systems. Springer New York. https://doi.org/10.1007/978-1-4614-0284-8
    Uchiyama K, Arakawa F, Kasahara H, Nojiri T, Noda H, Tawara Y et al. Heterogeneous multicore processor technologies for embedded systems. Springer New York, 2012. 224 p. https://doi.org/10.1007/978-1-4614-0284-8
    Uchiyama, Kunio ; Arakawa, Fumio ; Kasahara, Hironori ; Nojiri, Tohru ; Noda, Hideyuki ; Tawara, Yasuhiro ; Idehara, Akio ; Iwata, Kenichi ; Shikano, Hiroaki. / Heterogeneous multicore processor technologies for embedded systems. Springer New York, 2012. 224 p.
    @book{35dcc272ddae4bd2abe54029bae2e384,
    title = "Heterogeneous multicore processor technologies for embedded systems",
    abstract = "To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems; Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs; Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications.",
    author = "Kunio Uchiyama and Fumio Arakawa and Hironori Kasahara and Tohru Nojiri and Hideyuki Noda and Yasuhiro Tawara and Akio Idehara and Kenichi Iwata and Hiroaki Shikano",
    year = "2012",
    month = "10",
    day = "1",
    doi = "10.1007/978-1-4614-0284-8",
    language = "English",
    isbn = "9781461402848",
    publisher = "Springer New York",

    }

    TY - BOOK

    T1 - Heterogeneous multicore processor technologies for embedded systems

    AU - Uchiyama, Kunio

    AU - Arakawa, Fumio

    AU - Kasahara, Hironori

    AU - Nojiri, Tohru

    AU - Noda, Hideyuki

    AU - Tawara, Yasuhiro

    AU - Idehara, Akio

    AU - Iwata, Kenichi

    AU - Shikano, Hiroaki

    PY - 2012/10/1

    Y1 - 2012/10/1

    N2 - To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems; Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs; Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications.

    AB - To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems; Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs; Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications.

    UR - http://www.scopus.com/inward/record.url?scp=84949179289&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=84949179289&partnerID=8YFLogxK

    U2 - 10.1007/978-1-4614-0284-8

    DO - 10.1007/978-1-4614-0284-8

    M3 - Book

    AN - SCOPUS:84949179289

    SN - 9781461402848

    SN - 1461402832

    SN - 9781461402831

    BT - Heterogeneous multicore processor technologies for embedded systems

    PB - Springer New York

    ER -