Heterogeneous multiprocessor on a chip which enables 54x AAC-LC stereo encoding

Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Hiroshi Tanaka, Tomoyuki Kodama, Hiroaki Shikano, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    7 Citations (Scopus)

    Abstract

    A heterogeneous multiprocessor on a chip has been designed and implemented. It consists of 2 CPUs and 2 DRPs (Dynamic Reconfigurable Processors). The design of DRP was intended to achieve high-performance in a small area to be integrated on a SoC for embedded systems. Memory architecture of CPUs and DRPs were unified to improve programming and compiling efficiency. 54x AAC-LC stereo encoding has been enabled with 2 DRPs at 300MHz and 2 CPUs at 600MHz.

    Original languageEnglish
    Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
    Pages18-19
    Number of pages2
    DOIs
    Publication statusPublished - 2007
    Event2007 Symposium on VLSI Circuits, VLSIC - Kyoto
    Duration: 2007 Jun 142007 Jun 16

    Other

    Other2007 Symposium on VLSI Circuits, VLSIC
    CityKyoto
    Period07/6/1407/6/16

    Fingerprint

    Program processors
    Memory architecture
    Computer programming
    Embedded systems

    Keywords

    • Dynamic reconfigurable processor
    • Embedded system and AAC
    • Multiprocessor
    • SoC

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Ito, M., Todaka, T., Tsunoda, T., Tanaka, H., Kodama, T., Shikano, H., ... Kasahara, H. (2007). Heterogeneous multiprocessor on a chip which enables 54x AAC-LC stereo encoding. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. 18-19). [4342719] https://doi.org/10.1109/VLSIC.2007.4342719

    Heterogeneous multiprocessor on a chip which enables 54x AAC-LC stereo encoding. / Ito, Masaki; Todaka, Takashi; Tsunoda, Takanobu; Tanaka, Hiroshi; Kodama, Tomoyuki; Shikano, Hiroaki; Onouchi, Masafumi; Uchiyama, Kunio; Odaka, Toshihiko; Kamei, Tatsuya; Nagahama, Ei; Kusaoke, Manabu; Nitta, Yusuke; Wada, Yasutaka; Kimura, Keiji; Kasahara, Hironori.

    IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2007. p. 18-19 4342719.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Ito, M, Todaka, T, Tsunoda, T, Tanaka, H, Kodama, T, Shikano, H, Onouchi, M, Uchiyama, K, Odaka, T, Kamei, T, Nagahama, E, Kusaoke, M, Nitta, Y, Wada, Y, Kimura, K & Kasahara, H 2007, Heterogeneous multiprocessor on a chip which enables 54x AAC-LC stereo encoding. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 4342719, pp. 18-19, 2007 Symposium on VLSI Circuits, VLSIC, Kyoto, 07/6/14. https://doi.org/10.1109/VLSIC.2007.4342719
    Ito M, Todaka T, Tsunoda T, Tanaka H, Kodama T, Shikano H et al. Heterogeneous multiprocessor on a chip which enables 54x AAC-LC stereo encoding. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2007. p. 18-19. 4342719 https://doi.org/10.1109/VLSIC.2007.4342719
    Ito, Masaki ; Todaka, Takashi ; Tsunoda, Takanobu ; Tanaka, Hiroshi ; Kodama, Tomoyuki ; Shikano, Hiroaki ; Onouchi, Masafumi ; Uchiyama, Kunio ; Odaka, Toshihiko ; Kamei, Tatsuya ; Nagahama, Ei ; Kusaoke, Manabu ; Nitta, Yusuke ; Wada, Yasutaka ; Kimura, Keiji ; Kasahara, Hironori. / Heterogeneous multiprocessor on a chip which enables 54x AAC-LC stereo encoding. IEEE Symposium on VLSI Circuits, Digest of Technical Papers. 2007. pp. 18-19
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