High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization

N. Takenaka, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, Masahide Inuishi, T. Oashi, K. Tsukamoto

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

A high density Embedded DRAM technology has been developed with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC/SRAM. This technology includes (1)W/WNx poly-metal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-pluged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology can realizes both very small DRAM cell size of 0.29 μm2 and SRAM cell size of 2.77 μm2 on the same die.

Original languageEnglish
Pages (from-to)62-63
Number of pages2
JournalUnknown Journal
Publication statusPublished - 2000
Externally publishedYes

Fingerprint

Dynamic random access storage
Metallizing
electric contacts
Static random access storage
disposal
high aspect ratio
cells
metals
Aspect ratio
Metals

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Takenaka, N., Segawa, M., Uehara, T., Akamatsu, S., Matsumoto, M., Kurimoto, K., ... Tsukamoto, K. (2000). High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization. Unknown Journal, 62-63.

High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization. / Takenaka, N.; Segawa, M.; Uehara, T.; Akamatsu, S.; Matsumoto, M.; Kurimoto, K.; Ueda, T.; Watanabe, H.; Matsutani, T.; Yoneda, K.; Koshio, A.; Kato, Y.; Inuishi, Masahide; Oashi, T.; Tsukamoto, K.

In: Unknown Journal, 2000, p. 62-63.

Research output: Contribution to journalArticle

Takenaka, N, Segawa, M, Uehara, T, Akamatsu, S, Matsumoto, M, Kurimoto, K, Ueda, T, Watanabe, H, Matsutani, T, Yoneda, K, Koshio, A, Kato, Y, Inuishi, M, Oashi, T & Tsukamoto, K 2000, 'High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization', Unknown Journal, pp. 62-63.
Takenaka, N. ; Segawa, M. ; Uehara, T. ; Akamatsu, S. ; Matsumoto, M. ; Kurimoto, K. ; Ueda, T. ; Watanabe, H. ; Matsutani, T. ; Yoneda, K. ; Koshio, A. ; Kato, Y. ; Inuishi, Masahide ; Oashi, T. ; Tsukamoto, K. / High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization. In: Unknown Journal. 2000 ; pp. 62-63.
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abstract = "A high density Embedded DRAM technology has been developed with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC/SRAM. This technology includes (1)W/WNx poly-metal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-pluged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology can realizes both very small DRAM cell size of 0.29 μm2 and SRAM cell size of 2.77 μm2 on the same die.",
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AU - Takenaka, N.

AU - Segawa, M.

AU - Uehara, T.

AU - Akamatsu, S.

AU - Matsumoto, M.

AU - Kurimoto, K.

AU - Ueda, T.

AU - Watanabe, H.

AU - Matsutani, T.

AU - Yoneda, K.

AU - Koshio, A.

AU - Kato, Y.

AU - Inuishi, Masahide

AU - Oashi, T.

AU - Tsukamoto, K.

PY - 2000

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