High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization

N. Takenaka, M. Segawa, T. Uehara, S. Akamatsu, M. Matsumoto, K. Kurimoto, T. Ueda, H. Watanabe, T. Matsutani, K. Yoneda, A. Koshio, Y. Kato, M. Inuishi, T. Oashi, K. Tsukamoto

Research output: Contribution to journalConference article

10 Citations (Scopus)

Abstract

A high density Embedded DRAM technology has been developed with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC/SRAM. This technology includes (1)W/WNx poly-metal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-pluged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology can realizes both very small DRAM cell size of 0.29 μm2 and SRAM cell size of 2.77 μm2 on the same die.

Original languageEnglish
Pages (from-to)62-63
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
Publication statusPublished - 2000 Jan 1
Externally publishedYes
Event2000 Symposium on VLSI Technology - Honolulu, HI, USA
Duration: 2000 Jun 132000 Jun 15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Takenaka, N., Segawa, M., Uehara, T., Akamatsu, S., Matsumoto, M., Kurimoto, K., Ueda, T., Watanabe, H., Matsutani, T., Yoneda, K., Koshio, A., Kato, Y., Inuishi, M., Oashi, T., & Tsukamoto, K. (2000). High density embedded DRAM technology with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC by W/polySi gate and Cu dual damascene metallization. Digest of Technical Papers - Symposium on VLSI Technology, 62-63.