A high density Embedded DRAM technology has been developed with 0.38 μm pitch in DRAM and 0.42 μm pitch in LOGIC/SRAM. This technology includes (1)W/WNx poly-metal dual-gate with self aligned contacts (SAC) and disposal BPSG sidewall for fine design pitch, (2)W-pluged stacked contact structure for deep contact with high aspect ratio in DRAM region, (3)6-level Cu/TaN dual damascene metallization for fine pitch interconnect. This technology can realizes both very small DRAM cell size of 0.29 μm2 and SRAM cell size of 2.77 μm2 on the same die.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 2000 Jan 1|
|Event||2000 Symposium on VLSI Technology - Honolulu, HI, USA|
Duration: 2000 Jun 13 → 2000 Jun 15
ASJC Scopus subject areas
- Electrical and Electronic Engineering