High dependable implementation of neural networks with networks on chip architecture and a backtracking routing algorithm

Yiping Dong; Kento Kumai; Zhen Lin; Yinghe Li; Takahiro Watanabe

doi:10.1109/PRIMEASIA.2009.5397360

High dependable implementation of neural networks with networks on chip architecture and a backtracking routing algorithm

Yiping Dong^*, Kento Kumai, Zhen Lin, Yinghe Li, Takahiro Watanabe

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Networks on Chip (NoC), a new packet-based design method, with a new Dependable No Deadlock (DND) back-tracking routing algorithm are proposed to implement Artificial Neural Network (ANN). This system is simulated by NIRGAM NoC simulator to get system performance. Experimental results show that this proposed system has higher Connection-Per-Second (CPS), lower communication load than the exiting other implemented ANN. Furthermore this NoC implementation system is reconfigurable and expandable. In addition, this implementation method has a higher dependable than our former NoC implemented ANN system.

Original language	English
Title of host publication	1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009
Pages	404-407
Number of pages	4
DOIs	https://doi.org/10.1109/PRIMEASIA.2009.5397360
Publication status	Published - 2009 Dec 1
Externally published	Yes
Event	1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009 - Shanghai, China Duration: 2009 Nov 19 → 2009 Nov 21

Publication series

Name	1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009

Conference

Conference	1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009
Country/Territory	China
City	Shanghai
Period	09/11/19 → 09/11/21

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Education

Access to Document

10.1109/PRIMEASIA.2009.5397360

Cite this

Dong, Y., Kumai, K., Lin, Z., Li, Y., & Watanabe, T. (2009). High dependable implementation of neural networks with networks on chip architecture and a backtracking routing algorithm. In 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009 (pp. 404-407). [5397360] (1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009). https://doi.org/10.1109/PRIMEASIA.2009.5397360

High dependable implementation of neural networks with networks on chip architecture and a backtracking routing algorithm. / Dong, Yiping; Kumai, Kento; Lin, Zhen et al.

1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009. 2009. p. 404-407 5397360 (1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dong, Y, Kumai, K, Lin, Z, Li, Y & Watanabe, T 2009, High dependable implementation of neural networks with networks on chip architecture and a backtracking routing algorithm. in 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009., 5397360, 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009, pp. 404-407, 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009, Shanghai, China, 09/11/19. https://doi.org/10.1109/PRIMEASIA.2009.5397360

Dong Y, Kumai K, Lin Z, Li Y, Watanabe T. High dependable implementation of neural networks with networks on chip architecture and a backtracking routing algorithm. In 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009. 2009. p. 404-407. 5397360. (1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009). doi: 10.1109/PRIMEASIA.2009.5397360

Dong, Yiping ; Kumai, Kento ; Lin, Zhen et al. / High dependable implementation of neural networks with networks on chip architecture and a backtracking routing algorithm. 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009. 2009. pp. 404-407 (1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009).

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title = "High dependable implementation of neural networks with networks on chip architecture and a backtracking routing algorithm",

abstract = "Networks on Chip (NoC), a new packet-based design method, with a new Dependable No Deadlock (DND) back-tracking routing algorithm are proposed to implement Artificial Neural Network (ANN). This system is simulated by NIRGAM NoC simulator to get system performance. Experimental results show that this proposed system has higher Connection-Per-Second (CPS), lower communication load than the exiting other implemented ANN. Furthermore this NoC implementation system is reconfigurable and expandable. In addition, this implementation method has a higher dependable than our former NoC implemented ANN system.",

author = "Yiping Dong and Kento Kumai and Zhen Lin and Yinghe Li and Takahiro Watanabe",

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AB - Networks on Chip (NoC), a new packet-based design method, with a new Dependable No Deadlock (DND) back-tracking routing algorithm are proposed to implement Artificial Neural Network (ANN). This system is simulated by NIRGAM NoC simulator to get system performance. Experimental results show that this proposed system has higher Connection-Per-Second (CPS), lower communication load than the exiting other implemented ANN. Furthermore this NoC implementation system is reconfigurable and expandable. In addition, this implementation method has a higher dependable than our former NoC implemented ANN system.

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High dependable implementation of neural networks with networks on chip architecture and a backtracking routing algorithm

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