High dependable implementation of neural networks with networks on chip architecture and a backtracking routing algorithm

Yiping Dong, Kento Kumai, Zhen Lin, Yinghe Li, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Networks on Chip (NoC), a new packet-based design method, with a new Dependable No Deadlock (DND) back-tracking routing algorithm are proposed to implement Artificial Neural Network (ANN). This system is simulated by NIRGAM NoC simulator to get system performance. Experimental results show that this proposed system has higher Connection-Per-Second (CPS), lower communication load than the exiting other implemented ANN. Furthermore this NoC implementation system is reconfigurable and expandable. In addition, this implementation method has a higher dependable than our former NoC implemented ANN system.

Original languageEnglish
Title of host publication1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009
Pages404-407
Number of pages4
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009 - Shanghai
Duration: 2009 Nov 192009 Nov 21

Other

Other1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009
CityShanghai
Period09/11/1909/11/21

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Education

Cite this

Dong, Y., Kumai, K., Lin, Z., Li, Y., & Watanabe, T. (2009). High dependable implementation of neural networks with networks on chip architecture and a backtracking routing algorithm. In 1st Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2009 (pp. 404-407). [5397360] https://doi.org/10.1109/PRIMEASIA.2009.5397360