Abstract
The authors discuss an experimental 64-kb/s video codec that transmits still and motion pictures in several coding modes. In previous work (1986), they proposed a coding scheme, tailored to 384-kb/s transmission, that used motion-compensated prediction and hybrid quantization and a 64-kb/s video codec design concept having several coding modes. Here, they detail the computer simulation used to check the proposed coding scheme's efficiency at 64 kb/s. They then describe the hardware architecture that implements the design concept. The performance of the video codec is then demonstrated in different coding modes.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
| Place of Publication | Piscataway, NJ, United States |
| Publisher | Publ by IEEE |
| Pages | 2889-2892 |
| Number of pages | 4 |
| Volume | 3 |
| ISBN (Print) | 9517212410 |
| Publication status | Published - 1988 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials