HIGH LATCH-UP IMMUNITY FULL CMOS RAM.

K. Anami*, M. Yoshimoto, T. Yoshihara, S. Nagao, Y. Akasaka, T. Nakano

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Summary form only given. A solution for the latch-up problem in full CMOS RAM is proposed. The solution involves an improved power supply configuration in the memory cell. A well-source' structure is proposed in which the internal power source is provided through the N-well. Latch-up phenomena do not occur in the well-source structure, though latch-up phenomena are observed at voltage noises of plus 170 V, -1V or current noises of plus 670 mu mA, -180 mu mA.

Original languageEnglish
Title of host publicationDigest of Technical Papers - Symposium on VLSI Technology
Place of PublicationTokyo, Jpn
PublisherBusiness Cent for Academic Soc Japan
Pages12-13
Number of pages2
ISBN (Print)4930813085
Publication statusPublished - 1984
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)

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