HIGH LATCH-UP IMMUNITY FULL CMOS RAM.

K. Anami; M. Yoshimoto; T. Yoshihara; S. Nagao; Y. Akasaka; T. Nakano

HIGH LATCH-UP IMMUNITY FULL CMOS RAM.

K. Anami, M. Yoshimoto, T. Yoshihara, S. Nagao, Y. Akasaka, T. Nakano

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Summary form only given. A solution for the latch-up problem in full CMOS RAM is proposed. The solution involves an improved power supply configuration in the memory cell. A well-source' structure is proposed in which the internal power source is provided through the N-well. Latch-up phenomena do not occur in the well-source structure, though latch-up phenomena are observed at voltage noises of plus 170 V, -1V or current noises of plus 670 mu mA, -180 mu mA.

Original language	English
Title of host publication	Digest of Technical Papers - Symposium on VLSI Technology
Place of Publication	Tokyo, Jpn
Publisher	Business Cent for Academic Soc Japan
Pages	12-13
Number of pages	2
ISBN (Print)	4930813085
Publication status	Published - 1984
Externally published	Yes

ASJC Scopus subject areas

Engineering(all)

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Cite this

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title = "HIGH LATCH-UP IMMUNITY FULL CMOS RAM.",

abstract = "Summary form only given. A solution for the latch-up problem in full CMOS RAM is proposed. The solution involves an improved power supply configuration in the memory cell. A well-source' structure is proposed in which the internal power source is provided through the N-well. Latch-up phenomena do not occur in the well-source structure, though latch-up phenomena are observed at voltage noises of plus 170 V, -1V or current noises of plus 670 mu mA, -180 mu mA.",

author = "K. Anami and M. Yoshimoto and T. Yoshihara and S. Nagao and Y. Akasaka and T. Nakano",

year = "1984",

language = "English",

isbn = "4930813085",

pages = "12--13",

booktitle = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Business Cent for Academic Soc Japan",

}

TY - GEN

T1 - HIGH LATCH-UP IMMUNITY FULL CMOS RAM.

AU - Anami, K.

AU - Yoshimoto, M.

AU - Yoshihara, T.

AU - Nagao, S.

AU - Akasaka, Y.

AU - Nakano, T.

PY - 1984

Y1 - 1984

N2 - Summary form only given. A solution for the latch-up problem in full CMOS RAM is proposed. The solution involves an improved power supply configuration in the memory cell. A well-source' structure is proposed in which the internal power source is provided through the N-well. Latch-up phenomena do not occur in the well-source structure, though latch-up phenomena are observed at voltage noises of plus 170 V, -1V or current noises of plus 670 mu mA, -180 mu mA.

AB - Summary form only given. A solution for the latch-up problem in full CMOS RAM is proposed. The solution involves an improved power supply configuration in the memory cell. A well-source' structure is proposed in which the internal power source is provided through the N-well. Latch-up phenomena do not occur in the well-source structure, though latch-up phenomena are observed at voltage noises of plus 170 V, -1V or current noises of plus 670 mu mA, -180 mu mA.

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UR - http://www.scopus.com/inward/citedby.url?scp=0021640081&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0021640081

SN - 4930813085

SP - 12

EP - 13

BT - Digest of Technical Papers - Symposium on VLSI Technology

PB - Business Cent for Academic Soc Japan

CY - Tokyo, Jpn

ER -