Abstract
Summary form only given. A solution for the latch-up problem in full CMOS RAM is proposed. The solution involves an improved power supply configuration in the memory cell. A well-source' structure is proposed in which the internal power source is provided through the N-well. Latch-up phenomena do not occur in the well-source structure, though latch-up phenomena are observed at voltage noises of plus 170 V, -1V or current noises of plus 670 mu mA, -180 mu mA.
Original language | English |
---|---|
Title of host publication | Digest of Technical Papers - Symposium on VLSI Technology |
Place of Publication | Tokyo, Jpn |
Publisher | Business Cent for Academic Soc Japan |
Pages | 12-13 |
Number of pages | 2 |
ISBN (Print) | 4930813085 |
Publication status | Published - 1984 |
Externally published | Yes |
ASJC Scopus subject areas
- Engineering(all)