High-level area/delay/power estimation for low power system VLSIs with gated clocks

Shinichi Noda, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Contribution to journalArticle

    4 Citations (Scopus)

    Abstract

    At high-level synthesis for system VLSIs, their power consumption is efficiently reduced by applying gated clocks to them. Since using gated clocks causes the reduction of power consumption and the increase of area/delay, estimating trade-off between power and area/delay by applying gated clocks is very important. In this paper, we discuss the amount of variance of area, delay and power by applying gated clocks. We propose a simple gate-level circuit model and estimation equations. We vary parameters in our proposed circuit model, and evaluate power consumption by back-annotating gate-level simulation results to the original circuit. This paper also proposes a conditional expression for applying gated clocks. The expression shows whether or not we can reduce power consumption by applying gated clocks. We confirm the accuracy of proposed estimation equations by experiments.

    Original languageEnglish
    Pages (from-to)827-834
    Number of pages8
    JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    VolumeE85-A
    Issue number4
    Publication statusPublished - 2002 Apr

    Fingerprint

    Power System
    Power Consumption
    Clocks
    Electric power utilization
    High-level Synthesis
    Networks (circuits)
    Trade-offs
    Vary
    Evaluate
    Model
    Experiment
    Simulation
    Experiments

    Keywords

    • Gated clock
    • High-level synthesis
    • Power estimation
    • Sequential circuit
    • Switching activity

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Hardware and Architecture
    • Information Systems

    Cite this

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    abstract = "At high-level synthesis for system VLSIs, their power consumption is efficiently reduced by applying gated clocks to them. Since using gated clocks causes the reduction of power consumption and the increase of area/delay, estimating trade-off between power and area/delay by applying gated clocks is very important. In this paper, we discuss the amount of variance of area, delay and power by applying gated clocks. We propose a simple gate-level circuit model and estimation equations. We vary parameters in our proposed circuit model, and evaluate power consumption by back-annotating gate-level simulation results to the original circuit. This paper also proposes a conditional expression for applying gated clocks. The expression shows whether or not we can reduce power consumption by applying gated clocks. We confirm the accuracy of proposed estimation equations by experiments.",
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    AU - Noda, Shinichi

    AU - Togawa, Nozomu

    AU - Yanagisawa, Masao

    AU - Ohtsuki, Tatsuo

    PY - 2002/4

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    KW - Power estimation

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    KW - Switching activity

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