High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    9 Citations (Scopus)

    Abstract

    In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.

    Original languageEnglish
    Title of host publication2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
    Pages164-167
    Number of pages4
    DOIs
    Publication statusPublished - 2008
    Event2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu
    Duration: 2008 Apr 232008 Apr 25

    Other

    Other2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
    CityHsinchu
    Period08/4/2308/4/25

    Fingerprint

    Scheduling
    Networks (circuits)
    High level synthesis

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Ohchi, A., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2008). High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. In 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT (pp. 164-167). [4542438] https://doi.org/10.1109/VDAT.2008.4542438

    High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. / Ohchi, Akira; Togawa, Nozomu; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. p. 164-167 4542438.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Ohchi, A, Togawa, N, Yanagisawa, M & Ohtsuki, T 2008, High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. in 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT., 4542438, pp. 164-167, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, Hsinchu, 08/4/23. https://doi.org/10.1109/VDAT.2008.4542438
    Ohchi A, Togawa N, Yanagisawa M, Ohtsuki T. High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. In 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. p. 164-167. 4542438 https://doi.org/10.1109/VDAT.2008.4542438
    Ohchi, Akira ; Togawa, Nozomu ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. pp. 164-167
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