High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Akira Ohchi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

doi:10.1109/VDAT.2008.4542438

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Akira Ohchi^*, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

^*Corresponding author for this work

School of Fundamental Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.

Original language	English
Title of host publication	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages	164-167
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2008.4542438
Publication status	Published - 2008 Sept 5
Event	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan, Province of China Duration: 2008 Apr 23 → 2008 Apr 25

Publication series

Name	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Conference

Conference	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	08/4/23 → 08/4/25

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/VDAT.2008.4542438

Cite this

Ohchi, A., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2008). High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. In 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT (pp. 164-167). [4542438] (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT). https://doi.org/10.1109/VDAT.2008.4542438

High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. / Ohchi, Akira; Togawa, Nozomu ; Yanagisawa, Masao et al.

2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. p. 164-167 4542438 (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ohchi, A, Togawa, N , Yanagisawa, M & Ohtsuki, T 2008, High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. in 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT., 4542438, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, pp. 164-167, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, Hsinchu, Taiwan, Province of China, 08/4/23. https://doi.org/10.1109/VDAT.2008.4542438

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abstract = "In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.",

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N2 - In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.

AB - In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.

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High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

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