High-level synthesis algorithms with floorplaning for distributed/shared- register architectures

Akira Ohchi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)

Abstract

In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.

Original languageEnglish
Title of host publication2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages164-167
Number of pages4
DOIs
Publication statusPublished - 2008 Sep 5
Event2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan, Province of China
Duration: 2008 Apr 232008 Apr 25

Publication series

Name2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Conference

Conference2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
CountryTaiwan, Province of China
CityHsinchu
Period08/4/2308/4/25

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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    Ohchi, A., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2008). High-level synthesis algorithms with floorplaning for distributed/shared- register architectures. In 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT (pp. 164-167). [4542438] (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT). https://doi.org/10.1109/VDAT.2008.4542438