High-level synthesis system for digital signal processing based on enumerating data-flow graphs

Nozomu Togawa, Takafumi Hisaki, Masao Yanagisawa, Tatsuo Ohtsuki

    Research output: Chapter in Book/Report/Conference proceedingChapter

    1 Citation (Scopus)

    Abstract

    This paper proposes a high-level synthesis system for datapath design of digital signal processing hardwares. The system consists of four phases: (1) DFG (data-flow graph) generation, (2) scheduling, (3) resource binding, and (4) HDL (hardware description language) generation. In (1), the system does not generate only one best DFG representing a given behavioral description of a hardware, but more than one good DFGs representing it. In (2) and (3), several synthesis tools can be incorporated into the system depending on the required objectives. Thus we can obtain more than one datapath candidates for a behavioral description with their area and performance evaluation. In (4), the best datapath design is selected among those candidates and its hardware description is generated. The experimental results for applying the system to several benchmarks show the effectiveness and efficiency.

    Original languageEnglish
    Title of host publicationProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    Place of PublicationPiscataway, NJ, United States
    PublisherIEEE
    Pages265-274
    Number of pages10
    Publication statusPublished - 1998
    EventProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98) - Yokohama, Jpn
    Duration: 1998 Feb 101998 Feb 13

    Other

    OtherProceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98)
    CityYokohama, Jpn
    Period98/2/1098/2/13

    Fingerprint

    Data flow graphs
    Digital signal processing
    Hardware
    Computer hardware description languages
    Scheduling
    High level synthesis

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Togawa, N., Hisaki, T., Yanagisawa, M., & Ohtsuki, T. (1998). High-level synthesis system for digital signal processing based on enumerating data-flow graphs. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 265-274). Piscataway, NJ, United States: IEEE.

    High-level synthesis system for digital signal processing based on enumerating data-flow graphs. / Togawa, Nozomu; Hisaki, Takafumi; Yanagisawa, Masao; Ohtsuki, Tatsuo.

    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1998. p. 265-274.

    Research output: Chapter in Book/Report/Conference proceedingChapter

    Togawa, N, Hisaki, T, Yanagisawa, M & Ohtsuki, T 1998, High-level synthesis system for digital signal processing based on enumerating data-flow graphs. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. IEEE, Piscataway, NJ, United States, pp. 265-274, Proceedings of the 1998 3rd Conference of the Asia and South Pacific Design Automation (ASP-DAC '98), Yokohama, Jpn, 98/2/10.
    Togawa N, Hisaki T, Yanagisawa M, Ohtsuki T. High-level synthesis system for digital signal processing based on enumerating data-flow graphs. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States: IEEE. 1998. p. 265-274
    Togawa, Nozomu ; Hisaki, Takafumi ; Yanagisawa, Masao ; Ohtsuki, Tatsuo. / High-level synthesis system for digital signal processing based on enumerating data-flow graphs. Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC. Piscataway, NJ, United States : IEEE, 1998. pp. 265-274
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