High-level synthesis with post-silicon delay tuning for RDR architectures

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    In this paper, we propose a high-level synthesis algorithm with post-silicon delay tuning for RDR architectures. We first obtain a non-delayed scheduling/binding result and a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we have a delayed scheduling/binding result so that its latency cannot be increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.

    Original languageEnglish
    Title of host publicationISOCC 2013 - 2013 International SoC Design Conference
    PublisherIEEE Computer Society
    Pages194-197
    Number of pages4
    ISBN (Print)9781479911417
    DOIs
    Publication statusPublished - 2013
    Event2013 International SoC Design Conference, ISOCC 2013 - Busan
    Duration: 2013 Nov 172013 Nov 19

    Other

    Other2013 International SoC Design Conference, ISOCC 2013
    CityBusan
    Period13/11/1713/11/19

    Fingerprint

    Tuning
    Scheduling
    Silicon
    High level synthesis

    ASJC Scopus subject areas

    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Hagio, Y., Yanagisawa, M., & Togawa, N. (2013). High-level synthesis with post-silicon delay tuning for RDR architectures. In ISOCC 2013 - 2013 International SoC Design Conference (pp. 194-197). [6863970] IEEE Computer Society. https://doi.org/10.1109/ISOCC.2013.6863970

    High-level synthesis with post-silicon delay tuning for RDR architectures. / Hagio, Yuta; Yanagisawa, Masao; Togawa, Nozomu.

    ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. p. 194-197 6863970.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Hagio, Y, Yanagisawa, M & Togawa, N 2013, High-level synthesis with post-silicon delay tuning for RDR architectures. in ISOCC 2013 - 2013 International SoC Design Conference., 6863970, IEEE Computer Society, pp. 194-197, 2013 International SoC Design Conference, ISOCC 2013, Busan, 13/11/17. https://doi.org/10.1109/ISOCC.2013.6863970
    Hagio Y, Yanagisawa M, Togawa N. High-level synthesis with post-silicon delay tuning for RDR architectures. In ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society. 2013. p. 194-197. 6863970 https://doi.org/10.1109/ISOCC.2013.6863970
    Hagio, Yuta ; Yanagisawa, Masao ; Togawa, Nozomu. / High-level synthesis with post-silicon delay tuning for RDR architectures. ISOCC 2013 - 2013 International SoC Design Conference. IEEE Computer Society, 2013. pp. 194-197
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