TY - GEN
T1 - High-level synthesis with post-silicon delay tuning for RDR architectures
AU - Hagio, Yuta
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
PY - 2013/1/1
Y1 - 2013/1/1
N2 - In this paper, we propose a high-level synthesis algorithm with post-silicon delay tuning for RDR architectures. We first obtain a non-delayed scheduling/binding result and a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we have a delayed scheduling/binding result so that its latency cannot be increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.
AB - In this paper, we propose a high-level synthesis algorithm with post-silicon delay tuning for RDR architectures. We first obtain a non-delayed scheduling/binding result and a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we have a delayed scheduling/binding result so that its latency cannot be increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.
UR - http://www.scopus.com/inward/record.url?scp=84906895281&partnerID=8YFLogxK
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U2 - 10.1109/ISOCC.2013.6863970
DO - 10.1109/ISOCC.2013.6863970
M3 - Conference contribution
AN - SCOPUS:84906895281
SN - 9781479911417
T3 - ISOCC 2013 - 2013 International SoC Design Conference
SP - 194
EP - 197
BT - ISOCC 2013 - 2013 International SoC Design Conference
PB - IEEE Computer Society
T2 - 2013 International SoC Design Conference, ISOCC 2013
Y2 - 17 November 2013 through 19 November 2013
ER -