High-parallel LDPC decoder with power gating design

Ying Cui, Xiao Peng, Yu Jin, Peilin Liu, Shinji Kimura, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Leakage power is growing comparable to dynamic power dissipation as a result of technology trends, and thus it has become an important issue in low-power circuit design. As a popular technique for standby power reduction, power gating is applied to high-parallel LDPC decoder for WiMAX standard. The clustered-block processing engine (CBPE) array are divided into 9 power domains, and they are switched on or off according to different code lengths of LDPC code defined in WiMAX standard. As CBPE array occupies about 70% of the decoder system, the dedicated power gating strategy is very effective in shorter code length case since more power domains can be switched off. At shortest code length, power gating design brings about 55% power reduction compared to that of longest code length.

Original languageEnglish
Title of host publicationProceedings of International Conference on ASIC
Pages21-24
Number of pages4
DOIs
Publication statusPublished - 2011
Externally publishedYes
Event2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen
Duration: 2011 Oct 252011 Oct 28

Other

Other2011 IEEE 9th International Conference on ASIC, ASICON 2011
CityXiamen
Period11/10/2511/10/28

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Cui, Y., Peng, X., Jin, Y., Liu, P., Kimura, S., & Goto, S. (2011). High-parallel LDPC decoder with power gating design. In Proceedings of International Conference on ASIC (pp. 21-24). [6157112] https://doi.org/10.1109/ASICON.2011.6157112