High-parallel performance-aware LDPC decoder IP core design for WiMAX

Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    In this paper, we propose a synthesizable LDPC decoder IP core for the WiMAX system with high parallelism and enhanced error-correcting performance. The proposed fully-parallel layered decoder architecture can fully support multi-mode decoding specified in WiMAX with 12∼24 clock cycles for processing one iteration. By applying the 3-state processing schedule, it achieves twice parallelism with minor circuit area increase compared to state-of-the-art work, thus results in 46.8% improvement in power efficiency.

    Original languageEnglish
    Title of host publicationMidwest Symposium on Circuits and Systems
    Pages1136-1139
    Number of pages4
    DOIs
    Publication statusPublished - 2013
    Event2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 - Columbus, OH
    Duration: 2013 Aug 42013 Aug 7

    Other

    Other2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013
    CityColumbus, OH
    Period13/8/413/8/7

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    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

    Cite this

    Zhao, X., Chen, Z., Peng, X., Zhou, D., & Goto, S. (2013). High-parallel performance-aware LDPC decoder IP core design for WiMAX. In Midwest Symposium on Circuits and Systems (pp. 1136-1139). [6674853] https://doi.org/10.1109/MWSCAS.2013.6674853