High-parallel performance-aware LDPC decoder IP core design for WiMAX

Xiongxin Zhao; Zhixiang Chen; Xiao Peng; Dajiang Zhou; Satoshi Goto

doi:10.1109/MWSCAS.2013.6674853

High-parallel performance-aware LDPC decoder IP core design for WiMAX

Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

In this paper, we propose a synthesizable LDPC decoder IP core for the WiMAX system with high parallelism and enhanced error-correcting performance. The proposed fully-parallel layered decoder architecture can fully support multi-mode decoding specified in WiMAX with 12∼24 clock cycles for processing one iteration. By applying the 3-state processing schedule, it achieves twice parallelism with minor circuit area increase compared to state-of-the-art work, thus results in 46.8% improvement in power efficiency.

Original language	English
Title of host publication	Midwest Symposium on Circuits and Systems
Pages	1136-1139
Number of pages	4
DOIs	https://doi.org/10.1109/MWSCAS.2013.6674853
Publication status	Published - 2013
Event	2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 - Columbus, OH Duration: 2013 Aug 4 → 2013 Aug 7

Other

Other	2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013
City	Columbus, OH
Period	13/8/4 → 13/8/7

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/MWSCAS.2013.6674853

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title = "High-parallel performance-aware LDPC decoder IP core design for WiMAX",

abstract = "In this paper, we propose a synthesizable LDPC decoder IP core for the WiMAX system with high parallelism and enhanced error-correcting performance. The proposed fully-parallel layered decoder architecture can fully support multi-mode decoding specified in WiMAX with 12∼24 clock cycles for processing one iteration. By applying the 3-state processing schedule, it achieves twice parallelism with minor circuit area increase compared to state-of-the-art work, thus results in 46.8% improvement in power efficiency.",

author = "Xiongxin Zhao and Zhixiang Chen and Xiao Peng and Dajiang Zhou and Satoshi Goto",

year = "2013",

doi = "10.1109/MWSCAS.2013.6674853",

language = "English",

isbn = "9781479900664",

pages = "1136--1139",

booktitle = "Midwest Symposium on Circuits and Systems",

note = "2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 ; Conference date: 04-08-2013 Through 07-08-2013",

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T1 - High-parallel performance-aware LDPC decoder IP core design for WiMAX

AU - Zhao, Xiongxin

AU - Chen, Zhixiang

AU - Peng, Xiao

AU - Zhou, Dajiang

AU - Goto, Satoshi

PY - 2013

Y1 - 2013

N2 - In this paper, we propose a synthesizable LDPC decoder IP core for the WiMAX system with high parallelism and enhanced error-correcting performance. The proposed fully-parallel layered decoder architecture can fully support multi-mode decoding specified in WiMAX with 12∼24 clock cycles for processing one iteration. By applying the 3-state processing schedule, it achieves twice parallelism with minor circuit area increase compared to state-of-the-art work, thus results in 46.8% improvement in power efficiency.

AB - In this paper, we propose a synthesizable LDPC decoder IP core for the WiMAX system with high parallelism and enhanced error-correcting performance. The proposed fully-parallel layered decoder architecture can fully support multi-mode decoding specified in WiMAX with 12∼24 clock cycles for processing one iteration. By applying the 3-state processing schedule, it achieves twice parallelism with minor circuit area increase compared to state-of-the-art work, thus results in 46.8% improvement in power efficiency.

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U2 - 10.1109/MWSCAS.2013.6674853

DO - 10.1109/MWSCAS.2013.6674853

M3 - Conference contribution

AN - SCOPUS:84893196319

SN - 9781479900664

SP - 1136

EP - 1139

BT - Midwest Symposium on Circuits and Systems

T2 - 2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013

Y2 - 4 August 2013 through 7 August 2013

ER -

High-parallel performance-aware LDPC decoder IP core design for WiMAX

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