TY - GEN
T1 - High parallel variation banyan network based permutation network for reconfigurable LDPC decoder
AU - Peng, Xiao
AU - Chen, Zhixiang
AU - Zhao, Xiongxin
AU - Maehara, Fumiaki
AU - Goto, Satoshi
PY - 2010/8/27
Y1 - 2010/8/27
N2 - Permutation network plays an important role in the reconfigurable QC-LDPC decoder for most modern wireless communication systems with multiple code rates and various code lengths. In this paper, we propose the variation Banyan network (VBN) based permutation network architecture for the reconfigurable QC-LDPC decoders and give the control signal generating algorithm for cyclic shift. Through introducing the bypass network, we put forward the nonblocking scheme for any input number and shift number. In addition, the optimized VBN is proposed for WiMAX and WiFi standard, which can shift at most 4 groups of input data, and greatly reduce the hardware complexity. The synthesis results using the 90nm technology demonstrate that the proposed permutation network can be implemented with the gate count of 18.3k and the frequency of 600 MHz.
AB - Permutation network plays an important role in the reconfigurable QC-LDPC decoder for most modern wireless communication systems with multiple code rates and various code lengths. In this paper, we propose the variation Banyan network (VBN) based permutation network architecture for the reconfigurable QC-LDPC decoders and give the control signal generating algorithm for cyclic shift. Through introducing the bypass network, we put forward the nonblocking scheme for any input number and shift number. In addition, the optimized VBN is proposed for WiMAX and WiFi standard, which can shift at most 4 groups of input data, and greatly reduce the hardware complexity. The synthesis results using the 90nm technology demonstrate that the proposed permutation network can be implemented with the gate count of 18.3k and the frequency of 600 MHz.
KW - Banyan network
KW - LDPC decoder
KW - Permutation
KW - Reconfigurable
UR - http://www.scopus.com/inward/record.url?scp=77955901732&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77955901732&partnerID=8YFLogxK
U2 - 10.1109/ASAP.2010.5540964
DO - 10.1109/ASAP.2010.5540964
M3 - Conference contribution
AN - SCOPUS:77955901732
SN - 9781424469673
T3 - Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors
SP - 233
EP - 238
BT - ASAP 10 - 21st IEEE International Conference on Application-Specific Systems, Architectures and Processors, Conference Proceedings
T2 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2010
Y2 - 7 July 2010 through 9 July 2010
ER -