High-performance 0.5μm transistors

Research output: Contribution to journalArticle

Abstract

Sixteen-megabit dynamic RAMs (DRAMs) and four-megabit static RAMs (SRAMs) require a 0.5μm design rule to achieve a high integration scale. Along with such integration, 0.5μm devices have to achieve improved performance including high operating speed in circuits. However, submicron MOS transistors suffer from hot-carrier degradation and the short-channel effect. We have used the Mitsubishi Process Simulator (MIPS) and the Mitsubishi Device Simulation Program (MIDSIP) to clarify the internal state of 0.5μm transistors under operation to solve these problems and to develop 0.5μm transistors with improved electrical characteristics. The NMOS transistor features a lightly doped drain and the PMOS a buried-channel transistor.

Original languageEnglish
Pages (from-to)6-8
Number of pages3
JournalMitsubishi Electric Advance
Volume44
Publication statusPublished - 1988 Sep
Externally publishedYes

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Transistors
Random access storage
Hot carriers
MOSFET devices
Simulators
Degradation
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

High-performance 0.5μm transistors. / Inuishi, Masahide.

In: Mitsubishi Electric Advance, Vol. 44, 09.1988, p. 6-8.

Research output: Contribution to journalArticle

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