High performance and low latency mapping for neural network into network on chip architecture

Yiping Dong, Yang Wang, Zhen Lin, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Various hardware implementations of neural networks have been studied well in recent years. We have already proposed a hardware implementation method for neural network with a Network on Chip (NoC) architecture. A mapping of a neural network on NoC should be tuned to achieve high performance whenever neural network application is changed, so that different mapping methods are needed every time and tedious or burdensome works are required In this paper, we propose a general mapping strategy based on three rules. The mapping method with this strategy can implement different neural networks applications with NoC architecture. The simulation results show that the proposed method makes the system low latency and high performance.

Original languageEnglish
Title of host publicationASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC
Pages891-894
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha
Duration: 2009 Oct 202009 Oct 23

Other

Other2009 8th IEEE International Conference on ASIC, ASICON 2009
CityChangsha
Period09/10/2009/10/23

Fingerprint

Neural networks
Hardware
Network-on-chip

Keywords

  • Artificial neural network (ANN)
  • Hardware implementation
  • Mapping method
  • Network on Chip (NoC)
  • NoC architecture

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Dong, Y., Wang, Y., Lin, Z., & Watanabe, T. (2009). High performance and low latency mapping for neural network into network on chip architecture. In ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC (pp. 891-894). [5351550] https://doi.org/10.1109/ASICON.2009.5351550

High performance and low latency mapping for neural network into network on chip architecture. / Dong, Yiping; Wang, Yang; Lin, Zhen; Watanabe, Takahiro.

ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC. 2009. p. 891-894 5351550.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dong, Y, Wang, Y, Lin, Z & Watanabe, T 2009, High performance and low latency mapping for neural network into network on chip architecture. in ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC., 5351550, pp. 891-894, 2009 8th IEEE International Conference on ASIC, ASICON 2009, Changsha, 09/10/20. https://doi.org/10.1109/ASICON.2009.5351550
Dong Y, Wang Y, Lin Z, Watanabe T. High performance and low latency mapping for neural network into network on chip architecture. In ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC. 2009. p. 891-894. 5351550 https://doi.org/10.1109/ASICON.2009.5351550
Dong, Yiping ; Wang, Yang ; Lin, Zhen ; Watanabe, Takahiro. / High performance and low latency mapping for neural network into network on chip architecture. ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC. 2009. pp. 891-894
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