High performance autoassociative neural network using network on chip

Yiping Dong, Zhen Lin, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, an Artificial Autoassociative Neural Network (AANN) is implemented by Network on Chip (NoC) architecture to solve communication and performance problem. This proposed NoC based system can map four neurons in one PE and the whole system consists of PEs each of which connects with a router. This system is reconfigurable and extendable so that it can easily suit for different applications. Simulation results show that the proposed implementation method can reduce communication load and total computation time.

Original languageEnglish
Title of host publication2009 1st International Conference on Information Science and Engineering, ICISE 2009
Pages4015-4018
Number of pages4
DOIs
Publication statusPublished - 2009
Event1st International Conference on Information Science and Engineering, ICISE2009 - Nanjing
Duration: 2009 Dec 262009 Dec 28

Other

Other1st International Conference on Information Science and Engineering, ICISE2009
CityNanjing
Period09/12/2609/12/28

Fingerprint

Neural networks
Communication
Routers
Neurons
Network-on-chip

Keywords

  • Artificial Autoassociative Neural Network (AANN)
  • Communication load
  • Network on Chip (NoC)
  • NoC implementation method

ASJC Scopus subject areas

  • Information Systems

Cite this

Dong, Y., Lin, Z., & Watanabe, T. (2009). High performance autoassociative neural network using network on chip. In 2009 1st International Conference on Information Science and Engineering, ICISE 2009 (pp. 4015-4018). [5455373] https://doi.org/10.1109/ICISE.2009.633

High performance autoassociative neural network using network on chip. / Dong, Yiping; Lin, Zhen; Watanabe, Takahiro.

2009 1st International Conference on Information Science and Engineering, ICISE 2009. 2009. p. 4015-4018 5455373.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dong, Y, Lin, Z & Watanabe, T 2009, High performance autoassociative neural network using network on chip. in 2009 1st International Conference on Information Science and Engineering, ICISE 2009., 5455373, pp. 4015-4018, 1st International Conference on Information Science and Engineering, ICISE2009, Nanjing, 09/12/26. https://doi.org/10.1109/ICISE.2009.633
Dong Y, Lin Z, Watanabe T. High performance autoassociative neural network using network on chip. In 2009 1st International Conference on Information Science and Engineering, ICISE 2009. 2009. p. 4015-4018. 5455373 https://doi.org/10.1109/ICISE.2009.633
Dong, Yiping ; Lin, Zhen ; Watanabe, Takahiro. / High performance autoassociative neural network using network on chip. 2009 1st International Conference on Information Science and Engineering, ICISE 2009. 2009. pp. 4015-4018
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