Abstract
This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range. In our proposed stressless SOI DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can be relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage. Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM.
| Original language | English |
|---|---|
| Pages (from-to) | 1169-1178 |
| Number of pages | 10 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 35 |
| Issue number | 8 |
| DOIs | |
| Publication status | Published - 2000 Aug |
| Externally published | Yes |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
High-performance embedded SOI DRAM architecture for the low-power supply. / Yamauchi, Tadaaki; Morisita, Fukashi; Maeda, Shigenobu; Arimoto, Kazutami; Fujishima, Kazuyasu; Ozaki, Hideyuki; Yoshihara, Tsutomu.
In: IEEE Journal of Solid-State Circuits, Vol. 35, No. 8, 08.2000, p. 1169-1178.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - High-performance embedded SOI DRAM architecture for the low-power supply
AU - Yamauchi, Tadaaki
AU - Morisita, Fukashi
AU - Maeda, Shigenobu
AU - Arimoto, Kazutami
AU - Fujishima, Kazuyasu
AU - Ozaki, Hideyuki
AU - Yoshihara, Tsutomu
PY - 2000/8
Y1 - 2000/8
N2 - This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range. In our proposed stressless SOI DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can be relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage. Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM.
AB - This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the low voltage range. In our proposed stressless SOI DRAM array, the applied electric field to the gate oxide of the memory-cell transistor can be relaxed. The crucial problem that the gate oxide of the embedded-DRAM process must be thicker than that of the logic process can be solved. As a result, the performance degradation of the logic transistor can be avoided without forming the gate oxides of the memory-cell array and the logic circuits individually. In addition, the data retention characteristics can be improved. Secondly, we propose the body-bias-controlled SOI-circuit architecture which enhances the performance of the logic circuit at sub-1.2-V power supply voltage. Experimental results verify that the proposed circuit architecture has the potential to reduce the gate-delay time up to 30% compared to the conventional one. This proposed architecture could provide high performance in the low-voltage embedded SOI DRAM.
UR - http://www.scopus.com/inward/record.url?scp=0034248148&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0034248148&partnerID=8YFLogxK
U2 - 10.1109/4.859506
DO - 10.1109/4.859506
M3 - Article
AN - SCOPUS:0034248148
VL - 35
SP - 1169
EP - 1178
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 8
ER -