TY - GEN
T1 - High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels
AU - Dong, Yiping
AU - Lin, Zhen
AU - Li, Yan
AU - Watanabe, Takahiro
PY - 2010/8/31
Y1 - 2010/8/31
N2 - Hardware implementation of Artificial Neural Network (ANN) is proposed by using Networks on Chip (NoC) with 5-port 2-virtual channels router, aiming at higher performance and low latency. Experimental results by NIRGAM NoC simulator show that this proposed system has higher Connection-Per-Second (CPS), higher Connection-Per-Second-Per-Weight (CPSPW), lower communication load. Furthermore this NoC implementation system is reconfigurable and expandable, so that it can be applied to various applications.
AB - Hardware implementation of Artificial Neural Network (ANN) is proposed by using Networks on Chip (NoC) with 5-port 2-virtual channels router, aiming at higher performance and low latency. Experimental results by NIRGAM NoC simulator show that this proposed system has higher Connection-Per-Second (CPS), higher Connection-Per-Second-Per-Weight (CPSPW), lower communication load. Furthermore this NoC implementation system is reconfigurable and expandable, so that it can be applied to various applications.
UR - http://www.scopus.com/inward/record.url?scp=77955988993&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77955988993&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2010.5537747
DO - 10.1109/ISCAS.2010.5537747
M3 - Conference contribution
AN - SCOPUS:77955988993
SN - 9781424453085
T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
SP - 381
EP - 384
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Y2 - 30 May 2010 through 2 June 2010
ER -