High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels

Yiping Dong; Zhen Lin; Yan Li; Takahiro Watanabe

doi:10.1109/ISCAS.2010.5537747

High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels

Yiping Dong, Zhen Lin, Yan Li, Takahiro Watanabe

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Hardware implementation of Artificial Neural Network (ANN) is proposed by using Networks on Chip (NoC) with 5-port 2-virtual channels router, aiming at higher performance and low latency. Experimental results by NIRGAM NoC simulator show that this proposed system has higher Connection-Per-Second (CPS), higher Connection-Per-Second-Per-Weight (CPSPW), lower communication load. Furthermore this NoC implementation system is reconfigurable and expandable, so that it can be applied to various applications.

Original language	English
Title of host publication	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Nano-Bio Circuit Fabrics and Systems
Pages	381-384
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2010.5537747
Publication status	Published - 2010 Aug 31
Event	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France Duration: 2010 May 30 → 2010 Jun 2

Publication series

Name	ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Conference

Conference	2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Country	France
City	Paris
Period	10/5/30 → 10/6/2

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2010.5537747

Fingerprint Dive into the research topics of 'High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels'. Together they form a unique fingerprint.

Cite this

Dong, Y., Lin, Z., Li, Y., & Watanabe, T. (2010). High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 381-384). [5537747] (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537747

High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels. / Dong, Yiping; Lin, Zhen; Li, Yan; Watanabe, Takahiro.

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 381-384 5537747 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dong, Y, Lin, Z, Li, Y & Watanabe, T 2010, High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537747, ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, pp. 381-384, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 10/5/30. https://doi.org/10.1109/ISCAS.2010.5537747

Dong Y, Lin Z, Li Y, Watanabe T. High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 381-384. 5537747. (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems). https://doi.org/10.1109/ISCAS.2010.5537747

Dong, Yiping ; Lin, Zhen ; Li, Yan ; Watanabe, Takahiro. / High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 381-384 (ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems).

@inproceedings{8c16107c376f49b2b36b0a9a87f1e255,

title = "High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels",

abstract = "Hardware implementation of Artificial Neural Network (ANN) is proposed by using Networks on Chip (NoC) with 5-port 2-virtual channels router, aiming at higher performance and low latency. Experimental results by NIRGAM NoC simulator show that this proposed system has higher Connection-Per-Second (CPS), higher Connection-Per-Second-Per-Weight (CPSPW), lower communication load. Furthermore this NoC implementation system is reconfigurable and expandable, so that it can be applied to various applications.",

author = "Yiping Dong and Zhen Lin and Yan Li and Takahiro Watanabe",

year = "2010",

month = aug,

day = "31",

doi = "10.1109/ISCAS.2010.5537747",

language = "English",

isbn = "9781424453085",

series = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",

pages = "381--384",

booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems",

note = "2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 ; Conference date: 30-05-2010 Through 02-06-2010",

}

TY - GEN

T1 - High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels

AU - Dong, Yiping

AU - Lin, Zhen

AU - Li, Yan

AU - Watanabe, Takahiro

PY - 2010/8/31

Y1 - 2010/8/31

N2 - Hardware implementation of Artificial Neural Network (ANN) is proposed by using Networks on Chip (NoC) with 5-port 2-virtual channels router, aiming at higher performance and low latency. Experimental results by NIRGAM NoC simulator show that this proposed system has higher Connection-Per-Second (CPS), higher Connection-Per-Second-Per-Weight (CPSPW), lower communication load. Furthermore this NoC implementation system is reconfigurable and expandable, so that it can be applied to various applications.

AB - Hardware implementation of Artificial Neural Network (ANN) is proposed by using Networks on Chip (NoC) with 5-port 2-virtual channels router, aiming at higher performance and low latency. Experimental results by NIRGAM NoC simulator show that this proposed system has higher Connection-Per-Second (CPS), higher Connection-Per-Second-Per-Weight (CPSPW), lower communication load. Furthermore this NoC implementation system is reconfigurable and expandable, so that it can be applied to various applications.

UR - http://www.scopus.com/inward/record.url?scp=77955988993&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77955988993&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2010.5537747

DO - 10.1109/ISCAS.2010.5537747

M3 - Conference contribution

AN - SCOPUS:77955988993

SN - 9781424453085

T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

SP - 381

EP - 384

BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems

T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010

Y2 - 30 May 2010 through 2 June 2010

ER -