High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels

Yiping Dong, Zhen Lin, Yan Li, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Hardware implementation of Artificial Neural Network (ANN) is proposed by using Networks on Chip (NoC) with 5-port 2-virtual channels router, aiming at higher performance and low latency. Experimental results by NIRGAM NoC simulator show that this proposed system has higher Connection-Per-Second (CPS), higher Connection-Per-Second-Per-Weight (CPSPW), lower communication load. Furthermore this NoC implementation system is reconfigurable and expandable, so that it can be applied to various applications.

Original languageEnglish
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
Pages381-384
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris
Duration: 2010 May 30 → 2010 Jun 2

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CityParis
Period10/5/30 → 10/6/2

Fingerprint

Neural networks
Routers
Simulators
Hardware
Communication
Network-on-chip

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Dong, Y., Lin, Z., Li, Y., & Watanabe, T. (2010). High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 381-384). [5537747] https://doi.org/10.1109/ISCAS.2010.5537747

High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels. / Dong, Yiping; Lin, Zhen; Li, Yan; Watanabe, Takahiro.

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 381-384 5537747.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dong, Y, Lin, Z, Li, Y & Watanabe, T 2010, High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537747, pp. 381-384, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, 10/5/30. https://doi.org/10.1109/ISCAS.2010.5537747
Dong Y, Lin Z, Li Y, Watanabe T. High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 381-384. 5537747 https://doi.org/10.1109/ISCAS.2010.5537747
Dong, Yiping ; Lin, Zhen ; Li, Yan ; Watanabe, Takahiro. / High performance implementation of neural networks by networks on chip with 5-port 2-virtual channels. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 381-384
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