High performance networks on chip architecture with a new routing strategy for neural network

Yiping Dong; Zhen Lin; Takahiro Watanabe

doi:10.1109/PRIMEASIA.2010.5604890

High performance networks on chip architecture with a new routing strategy for neural network

Yiping Dong, Zhen Lin, Takahiro Watanabe

Graduate School of Information, Production and Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Hardware implementation by Networks on Chip (NoC) for Artificial Neural Network (ANN) was proposed to improve. In this work, a new architecture of NoC which has a hardware implementation of routing algorithm is proposed for ANN design. This routing strategy could reduce the packet size of header. The NOXIM NoC simulator is used to simulate the proposed system in term of latency, throughput and power consumption. The experimental results indicate that the proposed new NoC architecture is effective in increasing throughput and reducing latency and power consumption, compare with the traditional one. The ANN with the new NoC architecture could achieve higher performance and lower communication load.

Original language	English
Title of host publication	PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
Pages	347-350
Number of pages	4
DOIs	https://doi.org/10.1109/PRIMEASIA.2010.5604890
Publication status	Published - 2010 Dec 20
Event	2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010 - Shanghai, China Duration: 2010 Sep 22 → 2010 Sep 24

Publication series

Name	PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics

Conference

Conference	2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010
Country	China
City	Shanghai
Period	10/9/22 → 10/9/24

Fingerprint

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Dong, Y., Lin, Z., & Watanabe, T. (2010). High performance networks on chip architecture with a new routing strategy for neural network. In PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (pp. 347-350). [5604890] (PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics). https://doi.org/10.1109/PRIMEASIA.2010.5604890

High performance networks on chip architecture with a new routing strategy for neural network. / Dong, Yiping; Lin, Zhen; Watanabe, Takahiro.

PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. 2010. p. 347-350 5604890 (PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Dong, Y, Lin, Z & Watanabe, T 2010, High performance networks on chip architecture with a new routing strategy for neural network. in PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics., 5604890, PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, pp. 347-350, 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010, Shanghai, China, 10/9/22. https://doi.org/10.1109/PRIMEASIA.2010.5604890

Dong Y, Lin Z, Watanabe T. High performance networks on chip architecture with a new routing strategy for neural network. In PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. 2010. p. 347-350. 5604890. (PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics). https://doi.org/10.1109/PRIMEASIA.2010.5604890

Dong, Yiping ; Lin, Zhen ; Watanabe, Takahiro. / High performance networks on chip architecture with a new routing strategy for neural network. PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. 2010. pp. 347-350 (PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics).

@inproceedings{f2c9d857b10c46189a466afb54dd63f7,

title = "High performance networks on chip architecture with a new routing strategy for neural network",

abstract = "Hardware implementation by Networks on Chip (NoC) for Artificial Neural Network (ANN) was proposed to improve. In this work, a new architecture of NoC which has a hardware implementation of routing algorithm is proposed for ANN design. This routing strategy could reduce the packet size of header. The NOXIM NoC simulator is used to simulate the proposed system in term of latency, throughput and power consumption. The experimental results indicate that the proposed new NoC architecture is effective in increasing throughput and reducing latency and power consumption, compare with the traditional one. The ANN with the new NoC architecture could achieve higher performance and lower communication load.",

author = "Yiping Dong and Zhen Lin and Takahiro Watanabe",

year = "2010",

month = dec,

day = "20",

doi = "10.1109/PRIMEASIA.2010.5604890",

language = "English",

isbn = "9781424467372",

series = "PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics",

pages = "347--350",

booktitle = "PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics",

note = "2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010 ; Conference date: 22-09-2010 Through 24-09-2010",

}

TY - GEN

T1 - High performance networks on chip architecture with a new routing strategy for neural network

AU - Dong, Yiping

AU - Lin, Zhen

AU - Watanabe, Takahiro

PY - 2010/12/20

Y1 - 2010/12/20

N2 - Hardware implementation by Networks on Chip (NoC) for Artificial Neural Network (ANN) was proposed to improve. In this work, a new architecture of NoC which has a hardware implementation of routing algorithm is proposed for ANN design. This routing strategy could reduce the packet size of header. The NOXIM NoC simulator is used to simulate the proposed system in term of latency, throughput and power consumption. The experimental results indicate that the proposed new NoC architecture is effective in increasing throughput and reducing latency and power consumption, compare with the traditional one. The ANN with the new NoC architecture could achieve higher performance and lower communication load.

AB - Hardware implementation by Networks on Chip (NoC) for Artificial Neural Network (ANN) was proposed to improve. In this work, a new architecture of NoC which has a hardware implementation of routing algorithm is proposed for ANN design. This routing strategy could reduce the packet size of header. The NOXIM NoC simulator is used to simulate the proposed system in term of latency, throughput and power consumption. The experimental results indicate that the proposed new NoC architecture is effective in increasing throughput and reducing latency and power consumption, compare with the traditional one. The ANN with the new NoC architecture could achieve higher performance and lower communication load.

UR - http://www.scopus.com/inward/record.url?scp=78650111104&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=78650111104&partnerID=8YFLogxK

U2 - 10.1109/PRIMEASIA.2010.5604890

DO - 10.1109/PRIMEASIA.2010.5604890

M3 - Conference contribution

AN - SCOPUS:78650111104

SN - 9781424467372

T3 - PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics

SP - 347

EP - 350

BT - PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics

T2 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010

Y2 - 22 September 2010 through 24 September 2010

ER -

Access to Document

10.1109/PRIMEASIA.2010.5604890