Abstract
Hardware implementation by Networks on Chip (NoC) for Artificial Neural Network (ANN) was proposed to improve. In this work, a new architecture of NoC which has a hardware implementation of routing algorithm is proposed for ANN design. This routing strategy could reduce the packet size of header. The NOXIM NoC simulator is used to simulate the proposed system in term of latency, throughput and power consumption. The experimental results indicate that the proposed new NoC architecture is effective in increasing throughput and reducing latency and power consumption, compare with the traditional one. The ANN with the new NoC architecture could achieve higher performance and lower communication load.
| Original language | English |
|---|---|
| Title of host publication | PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics |
| Pages | 347-350 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2010 |
| Event | 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010 - Shanghai Duration: 2010 Sep 22 → 2010 Sep 24 |
Other
| Other | 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010 |
|---|---|
| City | Shanghai |
| Period | 10/9/22 → 10/9/24 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
High performance networks on chip architecture with a new routing strategy for neural network. / Dong, Yiping; Lin, Zhen; Watanabe, Takahiro.
PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. 2010. p. 347-350 5604890.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - High performance networks on chip architecture with a new routing strategy for neural network
AU - Dong, Yiping
AU - Lin, Zhen
AU - Watanabe, Takahiro
PY - 2010
Y1 - 2010
N2 - Hardware implementation by Networks on Chip (NoC) for Artificial Neural Network (ANN) was proposed to improve. In this work, a new architecture of NoC which has a hardware implementation of routing algorithm is proposed for ANN design. This routing strategy could reduce the packet size of header. The NOXIM NoC simulator is used to simulate the proposed system in term of latency, throughput and power consumption. The experimental results indicate that the proposed new NoC architecture is effective in increasing throughput and reducing latency and power consumption, compare with the traditional one. The ANN with the new NoC architecture could achieve higher performance and lower communication load.
AB - Hardware implementation by Networks on Chip (NoC) for Artificial Neural Network (ANN) was proposed to improve. In this work, a new architecture of NoC which has a hardware implementation of routing algorithm is proposed for ANN design. This routing strategy could reduce the packet size of header. The NOXIM NoC simulator is used to simulate the proposed system in term of latency, throughput and power consumption. The experimental results indicate that the proposed new NoC architecture is effective in increasing throughput and reducing latency and power consumption, compare with the traditional one. The ANN with the new NoC architecture could achieve higher performance and lower communication load.
UR - http://www.scopus.com/inward/record.url?scp=78650111104&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78650111104&partnerID=8YFLogxK
U2 - 10.1109/PRIMEASIA.2010.5604890
DO - 10.1109/PRIMEASIA.2010.5604890
M3 - Conference contribution
AN - SCOPUS:78650111104
SN - 9781424467372
SP - 347
EP - 350
BT - PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
ER -