High performance networks on chip architecture with a new routing strategy for neural network

Yiping Dong, Zhen Lin, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Hardware implementation by Networks on Chip (NoC) for Artificial Neural Network (ANN) was proposed to improve. In this work, a new architecture of NoC which has a hardware implementation of routing algorithm is proposed for ANN design. This routing strategy could reduce the packet size of header. The NOXIM NoC simulator is used to simulate the proposed system in term of latency, throughput and power consumption. The experimental results indicate that the proposed new NoC architecture is effective in increasing throughput and reducing latency and power consumption, compare with the traditional one. The ANN with the new NoC architecture could achieve higher performance and lower communication load.

Original languageEnglish
Title of host publicationPrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
Pages347-350
Number of pages4
DOIs
Publication statusPublished - 2010
Event2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010 - Shanghai
Duration: 2010 Sep 222010 Sep 24

Other

Other2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010
CityShanghai
Period10/9/2210/9/24

Fingerprint

Neural networks
Electric power utilization
Throughput
Hardware
Routing algorithms
Simulators
Network-on-chip
Communication

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Dong, Y., Lin, Z., & Watanabe, T. (2010). High performance networks on chip architecture with a new routing strategy for neural network. In PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (pp. 347-350). [5604890] https://doi.org/10.1109/PRIMEASIA.2010.5604890

High performance networks on chip architecture with a new routing strategy for neural network. / Dong, Yiping; Lin, Zhen; Watanabe, Takahiro.

PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. 2010. p. 347-350 5604890.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dong, Y, Lin, Z & Watanabe, T 2010, High performance networks on chip architecture with a new routing strategy for neural network. in PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics., 5604890, pp. 347-350, 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010, Shanghai, 10/9/22. https://doi.org/10.1109/PRIMEASIA.2010.5604890
Dong Y, Lin Z, Watanabe T. High performance networks on chip architecture with a new routing strategy for neural network. In PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. 2010. p. 347-350. 5604890 https://doi.org/10.1109/PRIMEASIA.2010.5604890
Dong, Yiping ; Lin, Zhen ; Watanabe, Takahiro. / High performance networks on chip architecture with a new routing strategy for neural network. PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. 2010. pp. 347-350
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