High performance NoC architecture for two hidden layers BP neural network

Yiping Dong, Takahiro Watanabe

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Artificial Neural Networks (ANNs)are widely used in applications of an intelligent system such as pattern recognition, fuzzy system, optimization and control. We have already proposed a novel NoC architecture for different kinds of BPANNs [1][2] and it was shown that the architecture is a promising hardware implementation for Neural Network. However, some problems to be solved are still remained. One of them is performance. In this paper, we propose another NoC architecture, network topology and routing strategy for higher performance. Experimental results by NoC simulator show that this new architecture and routing strategy reduce the communication load, reduce both latency by 7.7% and dynamic power consumption by 10.3% and also improve throughput by 8.1%, all compared with the previous one.

Original languageEnglish
Title of host publication2008 International SoC Design Conference, ISOCC 2008
PagesI269-I272
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
Duration: 2008 Nov 242008 Nov 25

Publication series

Name2008 International SoC Design Conference, ISOCC 2008
Volume1

Conference

Conference2008 International SoC Design Conference, ISOCC 2008
CountryKorea, Republic of
CityBusan
Period08/11/2408/11/25

Keywords

  • Architecture
  • Network on Chip
  • Neural Network

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

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  • Cite this

    Dong, Y., & Watanabe, T. (2008). High performance NoC architecture for two hidden layers BP neural network. In 2008 International SoC Design Conference, ISOCC 2008 (pp. I269-I272). [4815624] (2008 International SoC Design Conference, ISOCC 2008; Vol. 1). https://doi.org/10.1109/SOCDC.2008.4815624